• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.101-107
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• 1998

This paper is studied micro-defect characteristics by phosphorus 1MeV ion implantation and Rs, SRP, SIMS, XTEM for the RTA process was measured and simulated. As the dose is higher, the Rs is lower. When the dose are $1{\times}10^{13}/cm^2,\;5{\times}10^{13}/cm^2,\;1{\times}10^{14}/cm^2$, the Rp are $1.15{\mu}m,\;1.15{\mu},\;1.10{\mu}m$ respectively. As the RTA time is longer, the maximum concentration position is deeper from the surface and the concentration is lower. Before the RTA was done, we didn't observe any defect. But after the RTA process was done, we could observe the RTA process changed the micro-defects into the secondary defects. The simulation using the buried layer and connecting layer structure was performed. As results, the connecting layer had more effect than the buried layer to latch-up immune. Trigger current was more $0.6mA/{\mu}m$ and trigger voltage was 6V at dose $1{\times}10^{14}/cm^2$ and the energy 500KeV of connecting layer Lower connecting layer dose, latch-up immune characteristics was better.

• Journal of Korean Vacuum Science & Technology
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• v.4 no.2
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• pp.50-54
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• 2000

We studied the synthesis of S $i_{1-x}$ Cx (x=0.016) epitaxial layer using ion implantation and solid phase epitaxy (SPE). The activation energy Ea was obtained for the loss of substitutional carbon using fourier transform-infrared spectroscopy (FTIR) and high-resolution x-ray diffraction (HR-XRD). In FTIR analysis, the integrated peak intensity was used to quantify the loss of carbon atoms from substitutional to interstitial sites during annealing. The substitutional carbon contents in S $i_{0.984}$ $C_{0.016}$ were also measured using HR-XRD. By dynamic simulations of x-ray rocking curves, the fraction of substitutional carbon was obtained. The effects of annealing temperature and time were also studied by comparing vacuum furnace annealing with rapid thermal annealing (RTA))))))

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.562-565
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• 2001

In this paper, novel device structures in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA). Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20nm for arsenic dosage(2${\times}$10$\_$14//$\textrm{cm}^2$), exciter laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm and realized sub-50nm n-MOSFET.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.2
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• pp.48-54
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• 1999

We designed the optimal device parameters of the retrograde well and the gettering layer(buried layer) using the high energy ion implantation for the next generation of CMOS struoture and proposed two models and simulated these models with Athena and Atlas, Silvaco Co. We obtained trigger currents which is more than 600 ${\mu}A/{\mu}m$ when the structure has been combined the gettering layer and the retrograde well. And the second model(twin retrograde well) was obtained that holdingcurrents were over 2500${\mu}A/{\mu}m$. As results, the more heavier dose, the more improved the latch-up immunity. The n'-p' spacing was fixed a 2${\mu}m$ in both models.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.339-341
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• 1997

From this first studies, We have investigated the latch-up characteristics of various CMOS well structures possible with high energy ion implantation processes. In this study, we also investigated those of STI(Shallow Trench Isolation} structures with varing n+/p+ spacing and the depth of trench. STI structure is formed by T-SUPREM4 process simulator, and then latch-up simulations for each case were performed by MEDICI device simulator for latch-up immunity improvement. STI is very effective to preventing the degradation of latch-up characteristics as the n+/p+ spacing is reduced. These studies will allow us to evaluate each technology and suggest guidelines for the optimization of latch-up susceptibility.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.16-17
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• 2005

Local lifetime control by ion implantation has become an useful tool for production of modern power devices. In this work, punch-through diodes were irradiated with protons for the high speed power diode fabrication. Proton irradiation was executed at the various energy and dose conditions. Characterization of the device was performed by I-V, C-V and Trr measurement. We obtained enhanced reverse recovery time characteristics which was about 45% of original device and about 73% of electron irradiated device. The measurement results showed that proton irradiation was able to effectively reduce minority carrier lifetime.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.9
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• pp.700-704
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• 1998

In this paper, the optical properties of boron ion implanted GaAs were investigated by photoluminescence(PL) measurements. The implantations were preformed at room temperature with the energy of 150 eV. The range of implanted dose was $10^{12}~10^{15} ions/cm^2$. The boron implanted samples were annealed between $450^{\circ}C$ and $800^{\circ}C$ for 20 minutes. The crystallinity of low dosed samples were increased with increasing annealing temperature up to $700^{\circ}C$ while that of the high dosed($10^{15} ions/cm^2$) was almost same. From the samples with dose of $10^{14}~10^{15} ions/cm^2$, two emission bands were observed at 1.438 eV (B1) and 1.459 eV (B2) after the thermal treatment. These emission bands seems to be attributed to the $B_{Ga}$-defect complex.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.63-70
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• 1989

The ion beam extracted from the AuGe liquid metal ion source was implanted into GaAs substrate. The surface composition and the structure of ion implanted samples were investigated by AES, RHEED, SEM and EPMA. The depth profiles measured by AES were compared with the results of Monte Carlo simulation based on the two-body collision. As the results of AuGe ion implantation the preferential sputtering of As were revealed by AES and EPMA, and the outdiffusion of Ga and Ge was investigated by 300$^{circ}C$ annealing. The Au and Ge depth profiles measured by AES agreed with the results of Monte Carlo simulation based on the two-body collision.

• Electronics and Telecommunications Trends
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• v.5 no.1
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• pp.55-70
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• 1990

SIMOX SOI is known to be one of the most useful technologies for fabrications of new generation ULSI devices. This paper describes the current status of SIMOX SOI technology for ULSI applications. The SIMOX wafer is vertically composed of buried oxide layer and silicon epitaxial layer on top of the silicon substrate. The buried oxide layer is used for the vertical isolation of devices The oxide layer is formed by high energy ion implantation of high dose oxygen into the silicon wafer, followed by high temperature annealing. SIMOX-based CMOS fabrication is transparent to the conventional IC processing steps without well formation. Furthermore, thin film CMOX/SIMOX can overcome the technological limitations which encountered in submicron bulk-based CMOS devices, i.e., soft-error rate, subthreshold slope, threshold voltage roll-off, and hot electron degradation can be improved. SIMOX-based bipolar devices are expected to have high density which comparable to the CMOX circuits. Radiation hardness properties of SIMOX SOI extend its application fields to space and military devices, since military ICs should be operational in radiation-hardened and harsh environments. The cost of SIMOX wafer preparation is high at present, but it is expected to reduce as volume increases. Recent studies about SIMOX SOI technology have demonstrated that the performance of the SIMOX-based submicron devices is superior to the circuits using the bulk silicon.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.144-144
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• 2012

최근 폴리머를 기판으로 하는 고속 Flexible TFT (Thin film transistor)나 고효율의 박막 태양전지(Thin film solar cell)를 실현시키기 위해 낮은 비저항(resistivity)을 가지며, 높은 홀 속도(carrier hall mobility)와 긴 이동거리를 가지는 다결정 반도체 박막(poly-crystalline semiconductor thin film)을 만들고자 하고 있다. 지금까지 다결정 박막 반도체를 만들기 위해서는 비교적 높은 온도에서 장시간의 열처리가 필요했으며, 이는 폴리머 기판의 문제점을 야기시킬 뿐 아니라 공정시간이 길다는 단점이 있었다. 이에 반도체 박막의 재결정화 온도를 낮추어 주는 metal (Al, Ni, Co, Cu, Ag, Pd, etc.)을 이용하여 결정화시키는 방법(MIC)이 많이 연구되어지고 있지만, 이 또한 재결정화가 이루어진 반도체 박막 안에 잔류 금속(residual metal)이 존재하게 되어 비저항을 높이고, 홀 속도와 이동거리를 감소시키는 단점이 있다. 이에 본 실험은, 종래의 MIC 결정화 방법에서 이용되어진 금속 증착막을 이용하는 대신, HIPIMS (High power impulse magnetron sputtering)와 PIII&D (Plasma immersion ion implantation and deposition) 공정을 복합시킨 방법으로 적은 양의 알루미늄을 이온주입함으로써 재결정화 온도를 낮추었을 뿐 아니라, 잔류하는 금속의 양도 매우 적은 다결정 반도체 박막을 만들 수 있었다. 분석 장비로는 박막의 결정화도를 측정하기 위해 GIXRD (Glazing incident x-ray diffraction analysis)와 Raman 분광분석법을 사용하였고, 잔류하는 금속의 양과 화학적 결합 상태를 알아보기 위해 XPS (X-ray photoelectron spectroscopy)를 통한 분석을 하였다. 또한, 표면 상태와 막의 성장 상태를 확인하기 위하여 HRTEM(High resolution transmission electron microscopy)를 통하여 관찰하였다.