• 한국통신학회논문지
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• 제38C권3호
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• pp.311-317
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• 2013

본 논문에서는 멀티미디어 기반의 해상통신을 위한 DVB-S2 기반 고속 LDPC 복호를 위한 알고리즘을 제안하였다. 체크 노드 연산중에 비트 노드 연산을 수행하여 기존의 LDPC 복호 알고리즘에 비해 반복횟수를 줄일 수 있는 horizontal shuffle scheduling 알고리즘을 기반으로 하여 복호 속도를 보다 고속화 할 수 있는 알고리즘을 제안하였다. 기존의 체크 노드 연산은 하나의 메모리에서 값을 가져오기 때문에 체크 노드 연산과정에서 많은 지연이 발생하는데 이를 dc개의 병렬구조로 설계함으로써 체크 노드 연산과정의 지연을 줄일 수 있고 따라서 고속 복호가 가능하다. 이를 시뮬레이션 한 결과, 최대 반복 30회를 수행하였을 때 HSS 알고리즘은 326 Mbit/s, 제안한 알고리즘은 2.29 Gbit/s로 약 7배 이상의 복호 throughput을 얻을 수 있었다.

• 전자공학회논문지A
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• 제33A권7호
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• pp.34-43
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• 1996

In this paper a simpel algorithm for all-digial high speed symbol synchronization is proposed. The proposed algorithm has a structure based on BECM (band-edge component maximization). The algorithm requires only tow samples per symbol for its operation. We analyze and evaluate performance of the proposed algorithm. Simulation results reveal that the proposed algorithm has better performance than the gardner algorithm in narrowband.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.548-551
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• 2000

The battery charger for high speed trail car is very important power source for the purpose of safty and system stability. it provides control power of VVVF, CVCF, DC/DC converter and inverter for traction motor. This paper included power circuit of the ZVZCS type battery charger for high speed trail car and battery included power circuit of the ZVZCS type battery charger for high speed trail car and inverter for traction motor. This paper included power circuit of the ZVZCS type battery charger for high speed trail car an battery charging algorithm. Also the optimum parallel operation of 50Kw battery charger for high speed trail car and charging control method of Ni-Cd battery illustrates validity and effectiveness through the experiments.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.285-288
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• 2002

In this paper, a new structure of 1024-bit high-speed RSA cryptosystem has been proposed and implemented in hardware to increase the operation speed and enhance the variable-length operation in the plain text. The proposed algorithm applied a radix-4 Booth algorithm and CSA(Carry Save Adder) to the Montgomery algorithm for modular multiplication As the results from implementation, the clock period was approached to one delay of a full adder and the operation speed was 150MHz. The total amount of hardware was about 195k gates. The cryptosystem operates as the effective length of the inputted modulus number, which makes variable length encryption rather than the fixed-length one. Therefore, a high-speed variable-length RSA cryptosystem could be implemented.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.922-925
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• 2005

This article describes a FM modulation algorithm to increase the measurement speed by increasing the beat frequency of the laser without acousto-optic modulator(AOM) in the heterodyne laser interferometer. The proposed algorithm can increase the beat frequency of the heterodyne laser which limit the measurement speed by adjusting a carrier frequency through electronic circuit, while AOM is used to shift the frequency of the heterodyne laser in conventional method. Electronic circuit is constructed to modulate the signals from a laser interferometer and a waveform generator. The brier analysis, the measurement scheme of the system, and the experimental results using a Zeeman-stabilized He-Ne laser are presented. They demonstrate that the proposed algorithm is proven to enhance the measurement speed limit by increasing the beat frequency of the heterodyne laser.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부A
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• pp.182-185
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• 1998

This paper describes a field orientation control of an induction motor without any speed transducer and proposes a wide-range speed control strategy with the field orientation algorithm. The difference at impedances between the direct and quadrature axis at the injected signal is used for the sensorless field orientation control. But this algorithm has some limitations and should be supported by other method at high speed. In this paper, a sensorless speed control at an induction motor for wide speed range operation is proposed. The proposed algorithm is verified by experimental results.

• 한국통신학회논문지
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• 제30권6C호
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• pp.450-456
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• 2005

In this paper, we propose a high-speed turbo decoding algorithm and present results of its implementation. The latency caused by (de)interleaving and iterative decoding in conventional MAP turbo decoder can be dramatically reduced with the proposed scheme. The main cause of the time reduction is to use radix-4, center to top, and parallel decoding algorithm. The reduced latency makes it possible to use turbo decoder as a FEC scheme in the real-time wireless communication services. However the proposed scheme costs slight degradation in BER performance because the effective interleaver size in radix-4 is reduced to an half of that in conventional method. To ensure the time reduction, we implemented the proposed scheme on a FPGA chip and compared with conventional one in terms of decoding speed. The decoding speed of the proposed scheme is faster than conventional one at least by 5 times for a single iteration of turbo decoding.

• Journal of Power Electronics
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• 제5권1호
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• pp.11-19
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• 2005

This paper describes the two control techniques to perform the sensorless vector control of a PMSM by injecting the high frequency voltage to the stator terminal. The first technique is the estimation algorithm of the initial rotor position. A PMSM possesses the saliency which produces the ellipse of the stator current when the high frequency voltage is injected into the motor terminal. The major axis angle of the current ellipse gives the rotor position information at a standstill. The second control technique is a sensorless control algorithm that injects the high frequency voltage to the stator terminal in order to estimate the rotor position and speed. The rotor position and speed for sensorless vector control is calculated by appropriate signal processing to extract the position information from the stator current at low speeds or standstill. The proposed sensorless algorithm using the double-band hysteresis controller exhibits excellent reference tracking and increased robustness. Experimental results are presented to verify the feasibility of the proposed control schemes. Speed, position estimation and vector control were carried out on the floating point processor TMS320VC33.

• 대한전자공학회논문지SD
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• 제37권7호
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• pp.50-57
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• 2000

본 논문에서는 고속 FPGA 설계를 위한 논리 수준의 조합회로 합성 알고리듬을 제안한다. FPGA는 현장에서 직접 제작이 가능하고 제작 시간이 짧으며 제작 비용이 저렴하므로 초기 prototype 시스템의 제작에 자주 사용되고 있으나, ASIC 칩에 비해 지연시간이 크고 집적도가 떨어지는 단점이 있다. 제안된 알고리듬은 회로의 지연시간을 줄이기 위해 critical path를 분할한 후 분할된 회로를 동시에 수행하는 구조의 회로를 생성한다. MCNC 표준 테스트 회로에 대한 실험에서 제안된 지연시간 최적화 알고리듬이 기준 알고리듬에 비해 지연시간이 평균 19.1% 감소된 회로를 생성함을 보였다.

• 대한교통학회지
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• 제19권6호
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• pp.7-17
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• 2001

본 연구는 교통관리 시스템의 유고검지 체계를 검토하여 기존 체계의 문제점과 한계점을 극복할 수 있는 새로운 검지체계를 구축하고 새로 구축된 검지 체계에 맞는 알고리즘을 개발하는데 연구 목적이 있다. 새로운 검지체계는 검지기 1개소의 설치로 다차로를 검지할 수 있으며 특히 1개 차로 내에서도 검지영역을 여러 개 검지할 수 있는 다 검지체계의 장점을 최대한 살린 시스템이므로 기존 체계의 한계성인 단일 검지영역 문제를 해소할 수 있으며 경제적으로 교통관리 시스템을 구축할 수 있는 장점을 가지고 있다. 이 시스템으로 고속도로와 국도상에서 유고 검지율을 기존의 APID와 DES를 비교하여 현장 시험 평가한 결과 이 시스템이 제일 높은 유고 검지율을 나타내어 기존 시스템보다 우수한 것으로 판명되었다.