• 대한전기학회논문지
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• 제41권3호
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• pp.237-243
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• 1992

The large value of the snubber capacitor is needed to protect the devices in high voltage converters using series connected power semiconductors. But that results in more losses and longer commutation time. So, new technique of series connection is required, which can minimize the value of snubber capacitor and also promote the reliability of high voltage converters. We study on the switching characteristics of series connected power semiconductors and then propose a novel switching algorithm for series-connection which is able to implement not only the dynamic voltage balancing in spite of the differerce of switching characteristics, but the minimization of the value of snubber capacitor, through the change of the value of snubber capacitor by Miller effect. Finally, we illustrate the validity of this synchronization by computer simulation and experimental results.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제48권2호
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• pp.83-88
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• 1999

Series connection of power semiconductor devices is selected in high voltage and high power applications. It is important to prevent the overvoltage from being induced across a device above ratings by the proper voltage balancing in the field of IGBT series connection. In addition, the overvoltage induced by a stray inductance has to be limited in the high power circuit. This paper proposes a new gate control scheme which can balance the voltage properly and limit the overshoot by controlling the slope of collector voltage under the turn-off transient in the series connected IGBTs. The proposed gate control scheme changes the slope of collector voltage by sensing the collector voltage and controlling the gate signal actively. The new series connected IGBT gate driver is made and its validity is verified by the experimental results for series connected IGBT circuit.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2011년도 추계학술발표대회 논문집
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• pp.27-33
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• 2011

HCPV(High Concentrated PV) systems have well known for CPV market all over the world. Low concentration type silicon based modules have been introduced in the market. But low cost of standard flat silicon modules made them useless nowadays. High cost of compound semiconductor solar cell reduced cost effective cpv module production than that of recently silicon solar cell. In order to overcome increasing cost of CPV module, we study middle concentration type fresnel lens simulation using concentrated type silicon based solar cell. Linear type fresnel lens made production of CPV module without secondary optics such as light pipe or light tunnel. This type of fresnel lens design makes more cost effective solution for cpv niche market.

• 전기학회논문지P
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• 제52권4호
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• pp.172-178
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• 2003

This paper examines the application of high voltage static var compensator(SVC) with cascade multilevel inverter which employs H-bridge inverter(HBI). This method has the primary advantage that the number of voltage levels can be increased for a given number of semiconductor devices when compared to the conventional control methods. The SVC system is modeled using the d-q transform which calculates the instantaneous reactive power. This model is used to design a controller and analyze the SVC system. From the mathematical model of the system, the design procedures of the circuit parameters L and C are presented in this thesis. To meet the specific total harmonic distortion(THD) and ripple factor of the capacitor voltage, the circuit parameters L and C are designed. Simulated and experimental results are also presented and discussed to validate the proposed schemes.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.802-809
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• 2014

This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a $0.18-{\mu}m$ CMOS process for the 1.75 GHz band. For the 16-QAM LTE signal with a peak-to-average power ratio of 7.3 dB and a bandwidth of 5 MHz, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 dB, and an adjacent channel leakage power ratio of -30 dBc at an average output power of 22 dBm, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 dBm.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.688-696
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• 2014

A slew-rate control method of LCD driver ICs is introduced to increase uniformity between adjacent driver ICs and reduce power consumption. The slew rate of every voltage follower is calibrated by a feedback algorithm during the non-displaying period. Under normal operation mode, the slew rate is dynamically controlled for improving power efficiency. Experimental results show that the power consumption is reduced by 16% with a white pattern and by 10% with a black pattern, and display defects are successfully eliminated.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 하계학술대회 논문집
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• pp.596-599
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• 1991

This paper describes a novel switching algorithm of series connected power semiconductors for high voltage applications. In order to improve the reliability and efficiency of high voltage static power converters, we study on the switching characteristics of series connected power semiconductors and then propose "a servo control of snubber capacitor value" for the dynamic voltage balancing under turn-off state in series connected power semiconductors. Finally, we illustrate the validity of this algorithm by computer simulation and experimental results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.313-321
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• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.257-263
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• 2006

New charge pump circuits with low area and high power efficiency are proposed and verified in this paper. These pump circuits do not suffer the voltage stress higher than $V_{DD}$ across their pumping capacitors. Thus they can use the thin-oxide MOSFETs as the pumping capacitors. Using the thin-oxide capacitors can reduce the area of charge pumps greatly while keeping their driving capability. Comparing the new pump (NCP-2) with the conventional pump circuit using the thick-oxide capacitors shows that the power efficiency of NCP-2 is the same with the conventional one but the area efficiency of NCP-2 is improved as much as 71.8% over the conventional one, when the $V_{PP}/V_{DD}$ ratio is 3.5 and $V_{DD}$=1.8V.

• 한국전기전자재료학회논문지
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• 제15권12호
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• pp.1021-1026
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• 2002

As the development of semiconductor process technology continue to advance, ICs continue their trend toward higher performance low power system-on-chip (SOC). These circuits require on board multi power supply. In this paper, a 0.5 ㎛ dual date oxide CMOS Process technology for multi-power application is demonstrated. 5 V and 20 V devices fabricated by proposed process is measured. From 5 V devices using dual gate precess, we got almost the same characteristics as are obtained from standard 5 V devices. And the characteristics of the 20 V device demonstrates that 3 ㎛ devices with minimum gate length are available without reliability degradation. Electrical parameters in minimum 3 ㎛ devices are 520 ㎂/㎛ current density, 120 ㎷ DIBL, 24 V BV for NMOS and ,350 ㎂/㎛ current density, 180 ㎷ DIBL, 26 V BV for PMOS, respectively.