Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
권호 표지
DOI QR코드

DOI QR Code

A Study on the 0.5μm Dual Gate High Voltage CMOS Process for Si Liquid Display System

실리콘 액정표시 장치 시스템을 위한 00.5μm 이중 게이트 고전압 CMOS 공정 연구

  • Published : 2002.12.01
Download PDF
⟨ Previous Next ⟩

Abstract

As the development of semiconductor process technology continue to advance, ICs continue their trend toward higher performance low power system-on-chip (SOC). These circuits require on board multi power supply. In this paper, a 0.5 ㎛ dual date oxide CMOS Process technology for multi-power application is demonstrated. 5 V and 20 V devices fabricated by proposed process is measured. From 5 V devices using dual gate precess, we got almost the same characteristics as are obtained from standard 5 V devices. And the characteristics of the 20 V device demonstrates that 3 ㎛ devices with minimum gate length are available without reliability degradation. Electrical parameters in minimum 3 ㎛ devices are 520 ㎂/㎛ current density, 120 ㎷ DIBL, 24 V BV for NMOS and ,350 ㎂/㎛ current density, 180 ㎷ DIBL, 26 V BV for PMOS, respectively.

Keywords

References

  1. Proc. IEDM'98 Multiple gate oxide thickness for 2GHz system-on-A-Chip Technologies C. T. Lie;M. Oh
  2. Proc. CICC'98 High voltage CMOS LCD driver using low voltage CMOS process J. Haas;K. Au;L. C. Martin;T. L. Portlock;T. Sakurai
  3. 전기전자재료학회논문지 v.13 no.5 래치업 특성의 개선과 고속 스위칭 특성을 위한 다중 게이트 구조의 새로운 LIGBT 강이구;성만영
  4. ISPSD'98 High voltage SOI CMOS IC technology for driving plasma display panels Kenya Kobayashi;Hiroshi Yanagigawa
  5. Proc. VLSI Technology, Digest A high performance 30V extended drain RESULF CMOS device for VLSI intelligent power applications Peter C. Mei;Katsumi Fujikura;Takaaki Kawano;Satwinder Malhi
  6. 전기전자재료학회논문지 v.12 no.3 Deep 서브마이크론 LDD-nMOSFET의 핫캐리어현상 억제를 위한 반경험적인 LDD 공정 설계에 관한 연구 한태현;김남훈;김창일;서용진;장의구
  7. 대한전자공학회지 v.18 no.9 Submicron에서의 소자 기술 동향 신형순
  8. IEEE Circuits and Device Magazine Hot electron induced degradation of conventional, minimum overlap, LDD and DDD N channel MOSFETs Tian I Liou;Chih Sieh Teng;Richard B. Merrill
  9. Power Semiconductor Devices B. Jayant Baliga
  10. 전기전자재료학회논문지 v.13 no.2 고 에너지 이온 주입된 CMOS 쌍 우물 구조의 레치업 면역성 특성 예측을 위한 TCAD 모의실험 연구 김종민;송한정;곽계달
  11. AVANTI users manual(ver. 6.6) 2-dimensional process simulation program SUPREM-4
  12. 한국전지전자재료학회지 2000추계학술대회 v.13 no.1 멀티 오퍼레이션을 위한 0.5um Dual Gate 고전압 공정에 관한 연구 김진수;송한정;곽계달