• Journal of electromagnetic engineering and science
• /
• 제11권4호
• /
• pp.257-261
• /
• 2011

A highly efficient 2.4 GHz rectenna is designed using a harmonic rejection bandpass filter. The rectenna is printed on Rogers Duroid 5880 substrate with ${\varepsilon}_r$=2.2 and a thickness of 1.6 mm. The rectenna consists of a microstrip antenna and high order harmonic rejection bandpass filter, microstrip lowpass filter, and Schottky barrier diode (HSMS2820). The use of a $2^{nd}$ and $3^{rd}$ harmonic rejection microstrip bandpass filter in the rectenna results in high conversion efficiency. The proposed rectenna achieves a RF to DC conversion efficiency of 72.17 % when the received RF power is 63.09 mW.

• 한국전자파학회논문지
• /
• 제18권7호
• /
• pp.710-716
• /
• 2007

본 논문에서는 마이크로스트립 구조의 고조파 제거 회로를 이용하여 900 MHz 1 W 전력 증폭기 설계에 관하여 연구하였다. 기존의 전력 증폭기들에는 고조파 제거를 위하여 여러 단의 집중 정수 소자를 이용한 필터를 사용함으로써 회로의 크기가 커지고, 사용되는 마이크로스트림 선로의 경우 주파수의 반복적인 특성만을 나타냄으로써, 비선형 회로들의 출력에 존재하는 모든 고조파 성분들을 제거하지 못하는 단점을 개선한 것이다. 설계된 전력 증폭기는 구동 증폭단, 전력 증폭단 그리고 고조파 제거단으로 각각 구성하였고, 에폭시 기판에 하이브리드 형식으로 구현하였다. 구현된 전력 증폭기는 고조파 제거 회로를 부가하지 않았을 경우와 비교해서 24 dBc의 2차 고조파, 30 dBc의 3차 고조파의 감쇄 특성을 보였으며, 전력 증폭기와 안테나 사이의 출력단 필터를 대신할 수 있을 것으로 판단된다.

• ETRI Journal
• /
• 제30권2호
• /
• pp.344-346
• /
• 2008

In this paper, we present a novel oscillator (OSC) design. Bandpass filters, which can suppress harmonics, are incorporated into a co-design with an OSC to improve the OSC phase noise and harmonic rejection. The proposed OSC/bandpass filter co-design achieves a phase noise of -130.1 dBc/Hz/600 kHz and harmonic rejection of 37.94 dB and 40.85 dB for the second and third harmonics, respectively, as compared to results achieved by the OSC before co-design of -101.6 dBc/Hz/600 kHz and 21.28 dB and 19.68 dB. Good agreement between the measured and simulated results is achieved.

• Journal of electromagnetic engineering and science
• /
• 제14권2호
• /
• pp.47-53
• /
• 2014

This paper presents a high gain and high harmonic rejection low-noise amplifier (LNA) for software-defined radio receiver. This LNA exploits the high quality factor (Q) series resonance technique. High Q series resonance can amplify the in-band signal voltage and attenuate the out-band signals. This is achieved by a source impedance transformation. This technique does not consume power and can easily support multiband operation. The chip is fabricated in a $0.13-{\mu}m$ CMOS. It supports four bands (640, 710, 830, and 1,070MHz). The measured forward gain ($S_{21}$) is between 12.1 and 17.4 dB and the noise figure is between 2.7 and 3.3 dB. The IIP3 measures between -5.7 and -10.8 dBm, and the third harmonic rejection ratios are more than 30 dB. The LNA consumes 9.6 mW from a 1.2-V supply.

• 전자공학회논문지A
• /
• 제33A권10호
• /
• pp.81-89
• /
• 1996

In this paper, a very efficient CAD algorithm is proposedd where rhodes formulae combined with distributed lowpass prototype filter in order to design the corrugated waveguide harmonic rejection filters accurately. The proposed algorithm resolves effectively the problem of proximity effect without any optimiation or iterative design process by using the internally convexed corrugated structure. A 13-section tapered corrugated lowpass filter has been designed by the proposed algorithm and fabricated. The experimental results are in good agreement with the calculated results.

• Transactions on Electrical and Electronic Materials
• /
• 제17권4호
• /
• pp.217-221
• /
• 2016

In this work, open and short stubs that were fabricated on the silicon substrate and for which the periodically arrayed grounded-strip structure (PAGS) was employed were studied along with their basic RF characteristics for an applicability regarding the RF-matching components. The PAGS-employing open and short stubs showed losses that are much lower than that of the conventional stub on the silicon substrate. Concretely, the Q values of the open and short stubs are 9 and 10.2, respectively, while the Q value of the conventional open stub is 2.5. With the use of the PAGS-employing open and short stubs, a highly miniaturized harmonic-rejection filter was also fabricated on the silicon substrate. The filter exhibited a comparatively sound harmonic-suppression characteristic at n × 13 GHz, and its size is 0.1 mm², which is only 7% of the size of the conventional filter on the silicon substrate.

• KIEE International Transactions on Electrophysics and Applications
• /
• 제4C권6호
• /
• pp.272-275
• /
• 2004

A balanced single side-band (SSB) mixer employing a sub-harmonic configuration is designed for up and down conversions in K-band. The designed mixer uses anti-parallel diode (APD) pairs to effectively eliminate even harmonics of the local oscillator (LO) spurious signal. To reduce the odd harmonics of LO at the RF port, we employ a balanced configuration for LO. The fabricated chip shows 12$\pm$2dB of conversion loss and image-rejection ratio of about 20dB for down conversion at RF frequencies of 24-27.5GHz. As an up-conversion mode, the designed chip shows 12dB of conversion loss and image-rejection ratio of 20 ～ 25 dB at RF frequencies of 25 to 27GHz. The odd harmonics of the LO are measured below -37dBc.

• Journal of electromagnetic engineering and science
• /
• 제8권3호
• /
• pp.134-137
• /
• 2008

This paper proposes a novel quadrature VCO(QVCO) based on direct back-gate second harmonic coupling. The QVCO directly couples the current sources of the conventional LC VCOs through the back-gate instead of front-gate to generate quadrature signals. By the second harmonic injection locking, the two LC VCOs can generate quadrature signals without using on-chip transformer, or stability problem that is inherent in the direct front-gate second harmonic coupling. The proposed QVCO is implemented in $0.18{\mu}m$ CMOS technology operating at 2 GHz with 5.0 mA core current consumption from 1.8 V power supply. The measured phase noise of the proposed QVCO is - 63 dBc/Hz at 10 kHz offset, -95 dBc/Hz at 100 kHz offset, and -116 dBc/Hz at 1 MHz offset from the 2 GHz output frequency, respectively. The calculated figure of merit(FOM) is about -174 dBc/Hz at 1 MHz offset. The measured image band rejection is 46 dB which corresponds to the phase error of $0.6^{\circ}$.

• 융합신호처리학회논문지
• /
• 제4권1호
• /
• pp.41-48
• /
• 2003

본 논문에서는 DGS(Defected Ground Structure)에 대한 새로운 등가 회로를 제안하였으며, 이를 IMT-2000용 AB급 대전력 증폭기 설계에 적용하여 증폭기의 성능을 향상시켰다. 새로운 DGS 등가 회로는 병렬의 LC 공진기와 병렬 형태의 캐패시턴스로 구성되어 금속 접지면에 에칭된 결함으로 인한 프린징(fringing) 효과를 반영하도록 하였으며, 전력 증폭기 출 단 정합 회로를 최적화하기 위하여 사용되었다. 이전의 논문에서도 하모닉 성분의 억제와 증폭기의 효율 개선을 위하여 DGS를 사용하였으나 DGS 등가 회로의 해석은 없었으며(1), 본 논문에서는 이를 개선하여 회로 시뮬레이션을 통한 정한 DGS의 등가 회로를 AB급 증폭기의 출력 단 정합회로에 적용함으로써 성능 향상과 함께 증폭기 제작 후에 튜닝이 거의 필요없는 정확한 설계 방법을 제시하였다. 이와 같이 제안된 전력 증폭기의 설계 방법은 정확한 설계 결과를 제공함으로써 최적 부하 조건과 하모닉 성분의 제거 성능을 동시에 만족시킬 수 있었다. 제안된 방법의 효과를 입증하기 위하여 DGS를 적용한 기존의 방법과 새로이 제안된 방법을 사용하여 20W급의 전력 증폭기를 설계 및 제작하였으며, 그 측정 결과를 비교하였다.

• 한국통신학회논문지
• /
• 제21권12호
• /
• pp.3215-3226
• /
• 1996

In this paper a K-band harmonic oscillator competitive to ordinary Push-Push type oscillators is introduced. This oscillator is composed of two-X-band dielectric resonance circuits. To favor its harmonic generation, the load effect and the bias effect are studied to allow the maximum harmonic distortion. As results, the dielectric resonated load and the class A bias are used for the 2nd harmonic generation. analytical study for modelling of voltage controlled dielectric resonator is carried out with theoretical background. The performance of the circuit is evaluated by simulation using harmonic balanced method. The novel structure has ont only a voltage tuning circuit but also an output port at fundamental frequency as the function of prescaler for phase lockede loop application on the just single oscillation structure. In experimentation, the output freqneyc of the 2nd harmonic signal is 20.5GHz and the maximum power level of output is +5.5dBm without additional post amplifiers. the harmonic oscillator exhibits -30dBc of high fundamental frequency rejection without added extra filters. The phase noise of -90dBc/Hz at 100kHz off-carrier has been achieved under free running condition, that satisfies phase noise requirement of IESS 308. The proposed oscillator may be utilized as the clean and stable fixed local oscillator in Transmit Block Upconvertor(TBU) or Low oise Block downconvertor(LNB) for K/Ka-band digital communications and satellite broadcastings.