• Journal of Korean Society for Quality Management
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• v.29 no.4
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• pp.1-17
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• 2001

The characteristics of Telecommunication Industry encompass not only hardware and software but also the service aspect of them. One way to improve the industry up to the international level in terms of hardware and software as well as service aspect is to comply with tile TL 9000 standard, which was established by QUEST Forum, the group consisted of U.S. communication industry, based on the ISO 9000 Quality Management System. In this study, design, establishment, implementation, maintenance and improvement of quality system for domestic telecommunication industry are thoroughly investigated based on TL 9000 standard, with its LCM(Life Cycle Model) model and measurements. Also, Process Approach is suggested to help the industry realize the system to meet its specific needs. In addition, specific examples with the successful certification to TL 9000 standard are presented.

• The Journal of the Korea Contents Association
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• v.13 no.5
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• pp.408-419
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• 2013

The terminals of e-Book(electronic Book) are classified into two types which consist of special-purpose terminal equipment and general-purpose terminal equipment. Although the terminal products inr the two types have had a strong race in the e-Book market each other, both enterprises and consumers want the two type to remain persistently with competition in good faith. Therefore, it is necessary for each type camps to find blue ocean by establishing differentiation strategies of each type. In this paper, we designed the research model that independent variables consist of hardware quality and software quality, dependent variable is user satisfaction, moderator variable is the terminal type. Through the research model, we investigated factors having a influence on the user satisfaction of the e-Book terminal that consists of hardware and software. In particular, we investigated if the degree of the influence is different between the two types. As a result, we got conclusions as followings. First, the quality of hardware and software in the terminal had significant influences on the user satisfaction. Second, the degree which the hardware quality has influenced user satisfaction was not different between the two types, but the degree which the software quality has influence on user satisfaction was different between the two types. As a implication of this result, we found that special-purpose terminal provider need to establish a strategies for raising the quality of e-Book viewer to provide different product from general-purpose terminal.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.310-318
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• 2016

Emerging technologies such as the Internet of Things (IoT) and the Advanced Driver Assistant System (ADAS) often have image transmission functions with tough constraints, like low power and/or low delay, which require that they adopt line-based, low memory compression methods instead of existing frame-based image compression standards. Bit rate control in the conventional frame-based compression systems requires a lot of hardware resources when the scope of handled data falls at the frame level. On the other hand, attempts to reduce the heavy hardware resource requirement by focusing on line-level processing yield uneven image quality through the frame. In this paper, we propose a bit rate control that maintains consistency in image quality through the frame and improves the legibility of text regions. To find the line characteristics, the proposed bit rate control tests each line for ease of compression and the existence of text. Experiments on the proposed bit rate control show peak signal-to-noise ratios (PSNRs) similar to those of conventional bit rate controls, but with the use of significantly fewer hardware resources.

• Proceedings of the IEEK Conference
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• summer
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• pp.122-127
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• 2004

The color gamut mapping method that is used for enhancing the color reproduction quality between PC monitor and printer devices is adopted for display quality enhancement. The high definition display devices operate at the clock speed of around $70\;MHz\;\sim\;150\;MHz$ and permit several nano seconds for real-time processing. Thus, the concept of three-dimensional reduced resolution look-up table is used. The required hardware can be greatly reduced by look-up table resolution adjustment. The proposed hardware architecture is successfully implemented in ASIC and also successfully adopted in display quality enhancement purposes.

• International Journal of Quality Innovation
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• v.7 no.1
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• pp.90-97
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• 2006

The process of producing software differs in many aspects from that of traditional manufacturing. Software is not manufactured in the classical sense. Development of software more closely resembles the development effort that goes into design new product [1-3]. In this article, we first describe the foundations of process improvement, which all processes can share. The process improvement differences between software and manufacturing process are then discussed, and a defect driven process inspection and improvement is introduced. Based on the discussion, two experiments were designed and the results of the results were collected. Through the comparison, we found that some efficient quality improvement approaches can be easily adapted in the software improvement and that the inspection efficiency is also significant.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.22-34
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• 2010

Existing image scalers generally adopt simple interpolation methods such as bilinear method to take cost-benefit, or highly complex architectures to achieve high quality resulting images. However, demands for a low power, low cost, and high performance image scaler become more important because of emerging high quality mobile contents. In this paper we propose the novel low power hardware architecture for a high quality raster scan image scaler. The proposed scaler architecture enhances the existing cubic interpolation look-up table architecture by reducing and optimizing memory access and hardware components. The input data buffer of existing image scaler is replaced with line memories to reduce the number of memory access that is critical to power consumption. The cubic interpolation formula used in existing look-up table architecture is also rearranged to reduce the number of the multipliers and look-up table size. Finally we analyze the optimized parameter sets of look-up table, which is a trade-off between quality of result image and hardware size.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.112-118
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• 2014

As higher quality of image is required for digital image scaling, longer processing time is required. Therefore the technology that can make higher quality image quickly is needed. We propose the double linear-cubic convolution interpolation which creates the high quality image with low complexity and hardware resources. The proposed interpolation methods which are made up of four one-dimensional linear interpolations and one one-dimensional cubic convolution perform linear-cubic convolution interpolation in horizontal and vertical direction. When compared in aspects of peak signal-to-noise ratio(PSNR), performance time and amount of hardware resources, the proposed interpolation provided better PSNR, low complexity and less hardware resources than bicubic convolution interpolation.

• Proceedings of the KIEE Conference
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• 2002.11b
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• pp.127-130
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• 2002

Recently, with the increasing use of power semiconductors and microprocessors which are very sensitive to little change of power quality and for coping positively with anticipating power quality disputes between power providers and consumers which are possible to occur by of power market being formed, the power quality problem has gained preponderance among the contemporary research areas. To serve these purposes, the integrated system has been researched and developed for power quality analysis and monitoring, which provides speedy and powerful functions by the growth of computer hardware and information technology. But the advent of fast and lower price hardware make little difference in an application on many systems. As a result, the key issues of constructing power quality monitoring system are in the management of data obtained, accurate algorithms, graphic representation and user-friendly-environment for easy and clear analysis results. So, in this paper it will be introduced that the standard of user-friendly-GUI(Graphic User Interface) and analysis graphic representation for intuitive understanding of results from power quality analysis based on consideration of several systems currently being in use.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.192-197
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• 2017

In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.11
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• pp.1462-1467
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• 2018

A number of algorithms for improving the image quality of low light images have been studied using a single image or multiple exposure images. The low light image is low in contrast and has a large amount of noise, which limits the identification of information of the subject. This paper proposes the hardware design of algorithms that improve the quality of low light image using 2 multiple exposure images taken with a dual camera. The proposed hardware structure is designed in real time processing in a way that does not use frame memory and line memory using transfer function. The proposed hardware design has been designed using Verilog and validated in Modelsim. Finally, when the proposed algorithm is implemented on FPGA using xc7z045-2ffg900 as the target board, the maximum operating frequency is 167.617MHz. When the image size is 1920x1080, the total clock cycle time is 2,076,601 and can be processed in real time at 80.7fps.