Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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VLSI Architecture of Digital Image Scaler Combining Linear Interpolation and Cubic Convolution Interpolation

선형 보간법과 3차회선 보간법을 결합한 디지털 영상 스케일러의 VLSI 구조

  • Moon, Hae Min (Dept. of Information and Communication Engineering, Chosun University) ;
  • Pan, Sung Bum (Dept. of Electronics Engineering, Chosun University)
  • Received : 2013.10.14
  • Published : 2014.03.25
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Abstract

As higher quality of image is required for digital image scaling, longer processing time is required. Therefore the technology that can make higher quality image quickly is needed. We propose the double linear-cubic convolution interpolation which creates the high quality image with low complexity and hardware resources. The proposed interpolation methods which are made up of four one-dimensional linear interpolations and one one-dimensional cubic convolution perform linear-cubic convolution interpolation in horizontal and vertical direction. When compared in aspects of peak signal-to-noise ratio(PSNR), performance time and amount of hardware resources, the proposed interpolation provided better PSNR, low complexity and less hardware resources than bicubic convolution interpolation.

디지털 영상 확대를 위한 영상 스케일링은 고품질의 영상이 요구될수록 많은 수행시간 및 하드웨어 자원량이 요구된다. 본 논문에서는 적은 연산량 및 하드웨어 자원으로 고품질 영상을 생성하는 이중 선형-3차회선 보간법을 제안한다. 제안한 보간법은 4번의 선형 보간법과 1번의 3차회선 보간법으로 이루어진 선형-3차회선 보간법을 수평방향과 수직방향으로 각각 수행하는 구조이다. 실험결과, 제안하는 보간법은 PSNR과 수행시간 및 하드웨어 자원량 측면에서 비교했을 때, 적은 연산량 및 하드웨어 자원으로 양 3차회선 보간법보다 우수한 PSNR을 제공했다.

Keywords

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