• Journal of IKEEE
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• v.15 no.4
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• pp.267-273
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• 2011

In hardware design, its stability and reliability are important, because a hardware error can cause serious damages or disaster. To improve stability and reliability, this paper presents the implementation of the hardware verification system using the fault injection method in PC environment. This paper presents a verification platform that can verify hardware system reliably and effectively, through a process to generate faults as well as insert input signals into the actual running system environment. The verification system is configured to connect a PC with a digital I/O card, and it can transmit or receive signals from the target system, as a verifier's intention. In addition, it can generate faults and inject them into the target system. And it can be monitored by displaying the received signals from the target system to the graphical wave signals. We can evaluate its reliability by analyzing the graphical wave signals. In this paper, the proposed verification system has been applied to the FPGA firmware of a nuclear power plant control system. As a result, we found its usefulness and reliability.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.32-40
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• 2019

Indoor location estimation studies are needed in various fields. The method of estimating the indoor position can be divided into a method using hardware and a method using no hardware. The use of hardware is more accurate, but has the disadvantage of hardware installation costs. Conversely, the non-hardware method is not costly, but it is less accurate. To estimate the location for AR game, you need to get the solution of the Perspective-N-Point (PnP). To obtain the PnP problem, we need three-dimensional coordinates of the space in which we want to estimate the position and images taken in that space. The position can be estimated through six pairs of two-dimensional coordinates matching the three-dimensional coordinates. To further increase the accuracy of the solution, we proposed the use of an additional non-coplanarity degree to determine which points would increase accuracy. As the non-coplanarity degree increases, the accuracy of the position estimation becomes higher. The advantage of the proposed method is that it can be applied to all existing location estimation methods and that it has higher accuracy than hardware estimation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.1
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• pp.29-36
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• 2009

In this paper, we proposed auto exposure(AE) algorithm and hardware implementation for apply to mobile phone camera. AE is a function that control camera exposure automatically for appropriate to object. Existing AE is using micro controller unit and there are some problems about high expense and slow processing speed. For improve these problems, we proposed AE algorithm for hardware implementation without micro controller unit therefor we can expect improvement about the content of a production and operation speed. We proposed the algorithm that is considered efficiency of hardware resource and the results of hardware implementation of proposed AE algorithm apply to mobile phone camera sensor, we verified proposed AE function.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.80-86
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• 2002

This paper presents a fast hardware architecture to implement a 2-D DWT(Discrete Wavelet Transform) computed by lifting scheme framework. The conventional 2-D DWT hardware architecture has problem in internal memory, hardware resource, and latency. The proposed architecture was based on the 4-way partitioned data set. This architecture is configured with a pipelining parallel architecture for 4-way partitioning method. Due to the use of this architecture, total latency was improved by 50%, and memory size was reduced by using lifting scheme.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.67 no.1
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• pp.9-14
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• 2018

In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.926-932
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• 2007

Various research groups proposed various architecture of hardware VPN for the high performance VPN system. However, the VPN based on hardware researcher are focused only on the encryption acceleration. Soft based VPN is only useful when the network connection is slow. We have to consider the hardware performance (encryption/decryption processing capability, packet processing, architecture method) to implement hardware based VPN. In this paper, we have analysed architecture of hardware, consideration and problems for high-speed VPN system, From the result, we can choose the proper design guideline.

• Journal of IKEEE
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• v.27 no.3
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• pp.296-302
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• 2023

As Multimedia industry has evolved, it has become possible to display resolutions in various formats. Therefore, the performance of a scaler algorithm that converts resolutions while maintaining high quality and its hardware implementation are important. Considering the hardware design of an image up/down scaler, this paper proposes a combinatorial scaler algorithm that uses modified bilinear interpolation in the vertical direction and bicubic interpolation in the horizontal direction to reduce the line memory burden. Through quantitative and qualitative evaluations, this paper compared the performance of the proposed algorithm with three other well-known algorithms, and also compared the hardware burden of its hardware implementation. This paper used a sinusoidal signal and eight typical images for performance evaluation.

• Journal of IKEEE
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• v.18 no.4
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• pp.630-635
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• 2014

In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.

• Journal of Advanced Marine Engineering and Technology
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• v.28 no.2
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• pp.200-209
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• 2004

The fuzzy control based on $\alpha$-level fuzzy set decomposition. It is known to produce quick response and calculating time of fuzzy inference. This paper derived the embodiment computational algorithm for defuzzification by min-max fuzzy inference and the center of gravity method based on $\alpha$-level fuzzy set decomposition. It is easy to realize the fuzzy controller hardware. based on the calculation formula. In addition. this study proposed a circuit that generates PWM actual signals ranging from fuzzy inference to defuzzification. The fuzzy controller was implemented with mixed analog-digital logic circuit using the computational fuzzy inference algorithm by min-min-max and defuzzification by the center of gravity method. This study confirmed that the fuzzy controller worked satisfactorily when it was applied to the position control of a dc servo system.

• International Journal of Precision Engineering and Manufacturing
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• v.4 no.3
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• pp.28-35
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• 2003

The objective of the Vehicle Dynamics Control (VDC) system is to maintain vehicle stability under critical lateral motions, It has a good potential of becoming one of the chassis control necessities since the system can be realized with little additional cost on top of the ABS/TCS system, Developed in this research is a hardware-in-the-loop simulator for VDC with a valve control system that modulates the brake pressures at four wheels: Two VDC control logics, a simple control logic and an LQR control logic, have been developed and incorporated in the HILS system. Their performance under various driving conditions was tested in the HILS system and the results are presented.