• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.3
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• pp.343-348
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• 2014

Recently, applications of VSC-HVDC systems to power systems are growing because of their control ability of reactive power. Meanwhile, the hardware-in-the-loop simulation (HILS) based on the real-time digital simulator has been applying to develop and test imbedded controllers and systems in the power industry to decrease costs and to save time. In this paper, a 3-level neutral point clamped (NPC) VSC-HVDC system is modeled and the embedded controllers of the NPC VSC-HVDC system are designed. The designed controllers are implemented by TMS320F28335. The TMS320F28335-based controllers of the NPC VSC-HVDC system are tested using the HILS.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.42-45
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• 2012

A network processor (NP) is an application-specific instruction-set processor for fast and efficient packet processing. There are many issues in compiler's code generation and optimization due to NP's hardware constraints and special hardware support. In this paper, we describe in detail how to resolve the issues. Our compiler was developed on LLVM 3.0 and the NP target was our in-house network processor which consists of 32 64-bit RISC processors and supports multi-context with special hardware structures. Our compiler incurs only 9.36% code size overhead over hand-written code while satisfying QoS, and the generated code was tested on a real packet processing hardware, called S20 for code verification and performance evaluation.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.191-200
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• 2019

This study proposes a hardware-in-the-loop simulation (HILS) system based on National Instruments' PXI platform to test power management and operation strategies for DC microgrids (MGs). The HILS system is developed based on the controller HIL prototype, which involves testing the controller board in hardware with a real-time simulation model of the plant in a real-time digital simulator. The system provides an economical and effective testing function for research on MG systems. The decentralized power management strategy based on the DC bus signaling method for DC MGs has been developed and implemented on the HILS platform. HILS results are determined to be similar to those of the off-line simulation in PSIM software.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.95-98
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• 2004

In this paper, the hardware design of a transmission convergence sublayer(TC) for boradband wireless access system is described, which performs (1) formatting TC PDUs to MAC PDUs, (2) RS encoding/decoding, (3) providing various control signal to PHY modem. The TC hardware has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of electromagnetic engineering and science
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• v.9 no.1
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• pp.39-45
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• 2009

In this paper, we discuss hardware design and deployment issues in current passive UHF RFID systems. Using the link budget concept, the methodology to calculate forward- and reverse-link interrogation range is shown. Then, we consider hardware issues: phase diversity, phase noise with range correlation, and TX leakage problems. Finally, three interference problems when deploying RFID systems are presented.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.119-122
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• 2007

In this paper, we propose the method of hardware-design for the division operation of image frame-unit processing in mobile phone camera. Generally, there are two types of the data processing, which are the parallel and serial type. The parallel type makes it possible to process in realtime, but it needs significant hardware size due to many comparators and buffer memories. Compare the serial type with the parallel type, the hardware size of the serial type is smaller than the other because it uses only one comparator, but serial type is not able to process in realtime. To use the hardware resources efficiently, we employ the serial divider since frame-unit operation for image processing does not need realtime process. When compared with both in the same bit size and operating frequency, the hardware size of the serial divider is approximately in the ratio of 13 percentage compared with the parallel divider.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.670-673
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• 2008

Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP verified doubly in view of hardware structure together with algorithmic verification, was implemented on the Altera Excalibur FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2675-2680
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• 2010

Computation steps for 3D graphic processing consist of two stages - fixed operation stage and programming required stage. Using this characteristic of 3D pipeline, a hybrid structure between graphics hardware designed by fixed structure and programmable hardware based on instructions, can handle graphic processing more efficiently. In this paper, fragment Shader is designed under this hybrid structure. It also supports OpenGL ES 2.0. Interior interface is optimized to reduce the delay of entire pipeline, which may be occurred by data I/O between the fixed hardware and the Shader. Interior register group of the Shader is designed by an interleaved structure to improve the register space and processing speed.

• Korean Journal of Computational Design and Engineering
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• v.8 no.2
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• pp.65-74
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• 2003

For virtual reality, virtual manufacturing system, or simulation based design, we need to visualize very large and complex 3D models which are comprising of very large number of polygons. To overcome the limited hardware performance and to attain smooth realtime visualization, there have been many researches about algorithms which reduce the number of polygons to be processed by graphics hardware. One of these algorithms, occlusion culling is a method of rejecting the objects which are not visible because they are occluded by other objects, and then passing only the visible objects to graphics hardware. Existing occlusion culling algorithms have some shortcomings such as the required long preprocessing time, the limitation of occluder shape, or the need for special hardware implementation. In this study, an efficient occlusion culling algorithm is proposed. The proposed algorithm reads and analyzes Z-buffer of graphics hardware using Microsoft DirectX, and then determines each object's visibility. This proposed algorithm can speed up visualization by reading Z-buffer using DirectX which can access hardware directly compared to OpenGL, by reading only the region to which each object is projected instead of reading the whole Z-Buffer, and the proposed algorithm can perform more exact visibility test by using simplified model instead of using bounding box. For evaluation, the proposed algorithm was applied to very large polygonal models. And smooth realtime visualization was attained.

• Journal of IKEEE
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• v.23 no.3
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• pp.984-987
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• 2019

Recently, autonomous driving technology based on object recognition and lane recognition has attracted attention. However, in foggy weather, haze removal technology is needed because it is difficult to recognize surrounding objects. The technology of removing hazy is currently being studied in many ways, and a single image based haze removal algorithms are typical. In this paper, we design the hardware for haze removal by estimating the hazy partical map. Proposed hardware architecture is designed to have a cumulative histogram based filter that does not affect the hardware size even if the window size of filter increases. The hardware design is implemented with XILINX's xc7z045-ffg900 as the target board.