• Proceedings of the Korea Information Processing Society Conference
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• 2001.10a
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• pp.623-626
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• 2001

최근 휴대폰단말기, PDA 와 같은 내장형시스템에 필수적으로 사용되고 있는 SoC(System On a Chip)에 대한 설계에서는 HW/SW 동시설계를 통한 설계생산성 향상이 필수적이다. 이에 따라서 설계검증에서도 HW/SW 통합검증의 중요성이 매우 커지고 있다. 본 논문에서는 이와 같이 내장형시스템을 위한 HW/SW 통합검증을 효율적으로 수행 할 수 있는 방법들인 co-simulation 과 co-emulation 및 co-prototyping 에 대하여 이들 방법들의 장단점과 더불어 이들을 통합한 새로운 검증방법인 집적 동시-검증(integrated co-verification) 기법에 대하여 논하기로 한다.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.261-267
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• 2002

In SOC(System On a Chip) designs, reducing time and cast for design verification is the most critical to improve the design productivity. this is mainly because the designs require co-verifying HW together with SW, which results in the increase of verification complexity drastically. In this paper, to cope with the verification crisis in SOC designs, we propose a new verification methodology, so called integrated co-verification, which lightly combine both co-simulation and co-emulation in unified and seamless way. We have applied our integrated co-verification to ARM/AMBA platform-based co-verification environment with a commercial co-verification tool, Seamless CVE, and a physical prototyping board. The experiments has shown clear advantage of the proposed technique over conventional ones.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.274-279
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• 2009

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.396-399
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• 1999

In this paper, the efficient HW/SW co-simulation method which selects the ISA model dynamically is proposed. Because the ISA models with only fixed accuracy have been used in previous co-simulation environment, it may result in bad performance in speed or accuracy. In the proposed method, the cycle accurate ISA model is used in the case that the states of the detailed system are to be inspected. In other case, instruction-based model is executed in order to accelerate the simulation speed. The proposed dynamic model selection can be done by setting the conversion point in the application code before the simulation starts. The experiment on the embedded RISC processor have been performed, and its result shows that the proposed method is more efficient than the case of using fixed ISA model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.38-49
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• 2006

In this paper, a novel concept based on embedded processor and reconfigurable logic is proposed for efficient manufacturing test and design verification. Unlike traditional gap between design verification and manufacturing test, proposed concept is to combine both design verification and manufacturing test. The semiconductor chip which is using the proposed concept is named "SwToC" and SwToC stands for System with Test On a Chip. SwToC has two main features. First, it has functional verification function on a chip and this function could be made by using embedded processor, reconfigurable logic and memory. Second, it has internal ATE on a chip and this feature also could be made by the same architecture. To evaluate the proposed SwToC, we have implemented SwToC using commercial FPGA device with embedded processor. Experimental results showed that the proposed chip is possible for real application and could have faster verification time than traditional simulation method. Moreover, test could be done using low cost ATE.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.1
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• pp.49-60
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• 2005

The Back Bone of gearing portion between Core Network System which is used in wire and wireless system is No.7 Protocol. ISUP( ISDN User Part), INAP handling in Intelligent Network and MAP gearing method for linking each Network Element System in mobile network have use of No.7 signaling. Therefore, it is require for system to detect the problem - operating problem occurs in Core Network which use No.7 signaling or the existing problem that is not recognized - in shortest time. This paper study out analyzing and measuring system for No.7 protocol and analyzing out system whether out of order or not. It can abstract No.7 Signaling Message and analyze system performance and report it. This system is connected in system No.7 HW Module which is in charge of No.7 Signaling. It is not offer Emulator function and Simulation function for any scenario but offer monitoring No.7 signaling. This system perform the function about No.7 MTP, ISUP, INAP and MAP and is offered several wire and wireless network Operator. It can detect and correct SW system, HW system and operating system problem. From now on, this system may offer the function about A-interface which is gearing between BSC and MSC, so it will perform to analyze generally and prompt effective operating for Core Network system.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.376-382
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• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.