• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.229-236
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• 2017

This paper deals with the design and implementation of an efficient topology for cascaded multilevel inverters with reduced part counts. In the proposed design, a well-established basic unit is first developed. The series extension of this unit results in the formation of the proposed multilevel inverter. The proposed design minimizes the number of power electronic components including insulated-gate bipolar transistors and gate driver circuits, which in turn cuts down the size of the inverter assembly and reduces the operating power losses. An explicit control strategy with enhanced device efficiency is also acquired. Thus, the part count reductions enhance not only the economical merits but also the technical features of the entire system. In order to accomplish the desired operational aspects, three algorithms are considered to determine the magnitudes of the dc voltage sources effectively. The proposed topology is compared with the conventional cascaded H-bridge multilevel inverter topology, to reflect the merits of the presented structure. In continue, both the analytical and experimental results of a cascaded 31-level structure are analyzed. The obtained results are discussed in depth, and the exemplary performance of the proposed structure is corroborated.

• Journal of Power Electronics
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• v.13 no.2
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• pp.296-303
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• 2013

This paper proposes a high efficiency three-phase cascaded phase shifted H-bridge multi-level inverter without DC/DC converters for grid-tied multi string photovoltaic (PV) applications. The cascaded H-bridge topology is suitable for PV applications since each PV module can act as a separate DC source for each cascaded H-bridge module. The proposed phase shifted H-bridge multi-level topology offers advantages such as operation at a lower switching frequency and a lower current ripple when compared to conventional two level topologies. It is also shown that low ripple sinusoidal current waveforms are generated with a unity power factor. The control algorithm permits the independent control of each DC link voltage with a maximum power point for each string of PV modules. The use of the controller area network (CAN) communication protocol for H-bridge multi-level inverters, along with localized PWM generation and PV voltage regulation are implemented. It is also shown that the expansion and modularization capabilities of the H-bridge modules are improved since the individual inverter modules operate more independently. The proposed topology is implemented for a three phase 240kW multi-level PV power conditioning system (PCS) which has 40kW H-bridge modules. The experimental results show that the proposed topology has good performance.

• Journal of Power Electronics
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• v.17 no.1
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• pp.76-87
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• 2017

Finite-set predictive current control (FS-PCC) is advantageous for power converters due to its high dynamic performance and has received increasing interest in multilevel inverters. Among multilevel inverter topologies, the cascaded H-bridge (CHB) inverter is popular and mature in the industry. However, a main drawback of FS-PCC is its large computational burden, especially for the application of CHB inverters. In this paper, an FS-PCC method based on a deadbeat solution for three-phase zero-common-mode-voltage CHB inverters is proposed. In the proposed method, an inverse model of the load is utilized to calculate the reference voltage based on the reference current. In addition, a cost function is directly expressed in the terms of the voltage errors. An optimal control actuation is selected by minimizing the cost function. In the proposed method, only three instead of all of the control actuations are used for the calculations in one sampling period. This leads to a significant reduction in computations. The proposed method is tested on a three-phase 5-level CHB inverter. Simulation and experimental results show a very similar and comparable control performance from the proposed method compared with the traditional FS-PCC method which evaluates the cost function for all of the control actuations.

• Journal of Power Electronics
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• v.18 no.1
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• pp.56-69
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• 2018

In this paper, an improved Space Vector Modulation (SVM) based fault tolerant operation on a nine-level Cascaded H-Bridge (CHB) inverter with an additional backup circuit is proposed. Any type of fault in a power converter may result in a power interruption and productivity loss. Three different faults on H-bridge modules in all three phases based on the SVM approach are investigated with diagrams. Any fault in an inverter phase creates an unbalanced output voltage, which can lead to instability in the system. An additional auxiliary unit is connected in series to the three phase cascaded H-bridge circuit. With the help of this and the redundant switching states in SVM, the CHB inverter produces a balanced output with low harmonic distortion. This ensures high DC bus utilization under numerous fault conditions in three phases, which improves the system reliability. Simulation results are presented on three phase nine-level inverter with the automatic fault detection algorithm in the MATLAB/SIMULINK software tool, and experimental results are presented with DSP on five-level inverter to validate the practicality of the proposed SVM fault tolerance strategy on a CHB inverter with an auxiliary circuit.

• Journal of Power Electronics
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• v.15 no.3
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• pp.830-840
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• 2015

The H-bridge inverter is the fundamental power cell of the cascaded distribution static synchronous compensator (DSTATCOM). Thus, cell reliability is important to the compensation performance and stability of the overall system. The concept of the power electronics building block (PEBB) is an ideal solution for the power cell design. In this paper, an H-bridge inverter-based “plug and play” HPEBB is introduced into the main circuit and the controller to improve the compensation performance and reliability of the device. The section that discusses the main circuit primarily emphasizes the design of electrical parameters, physical structure, and thermal dissipation. The section that presents the controller part focuses on the principle of complex programmable logic device -based universal controller This section also analyzes typical reliability and anti-interference issues. The function and reliability of HPEBB are verified by experiments that are conducted on an HPEBB test-bed and on a 10 kV/± 10 Mvar DSTATCOM industrial prototype.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1074-1086
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• 2019

This paper presents the design and implementation of an improved cascaded multilevel inverter topology with asymmetric DC sources. This experimental inverter topology is a stand-alone system with simulations and experiments performed using resistance loads. The topology uses four asymmetric binary DC sources that are independent from each other and one H-bridge. The topology was simulated using PSIM software before an actual prototype circuit was tested. The proposed topology was shown to be very efficient. It was able to generate a smooth output waveform up to 31 levels with only eight switches. The obtained simulation and experimental results are almost identical. In a 1,200W ($48.3{\Omega}$) resistive load application, the THDv and efficiency of the topology were found to be 1.7% and 97%, respectively. In inductive load applications, the THDv values were 1.1% and 1.3% for an inductive load ($R=54{\Omega}$ dan L=146mH) and a 36W fluorescent lamp load with a capacitor connected at the dc bus.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.5
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• pp.376-380
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• 2010

This paper presents a circuit configuration of multilevel inverter to increase the number of output voltage levels by using conventional 5-level inverters connected in series. Most of all it can maximize the number of output voltage levels by employing input voltage sources, which have the power of five. When it synthesizes the same number of output voltage levels, the proposed inverter can save the number of switching devices compared with the conventional cascaded H-bridge cell inverter. So it can reduce the size, cost, power consumption of the system. We implemented computer-aided simulation and experiments for a 25-level inverter employing two 5-level inverters.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.61-62
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• 2012

본 논문에서는 다중 반송파 정현 펄스폭 변조방식으로 제어되는 Cascaded H-bridge 멀티레벨 PWM 인버터의 스위칭 손실 저감을 위한 스위칭 패턴을 제안한다. 부하 담당 전력이 상대적으로 큰 H-bridge 모듈의 스위치는 저주파의 기본 출력 전압 레벨을 형성하도록 동작시키며, 부하 담당 전력이 상대적으로 작은 H-bridge 모듈의 스위치는 고주파의 PWM 파형을 기본파에 가감하여 출력전압 파형이 사인파에 가까워지도록 스위칭 패턴을 형성한다. 본 논문에서는 제안된 스위칭 패턴을 PD, APOD 방식의 다중 반송파 정현 펄스폭 변조방식으로 구현하여 Cascaded H-bridge 멀티레벨 PWM 인버터에 적용시키고 실험을 통해 기존의 스위칭 패턴에 비해 스위칭 손실이 개선됨을 증명한다.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.496-497
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• 2014

본 논문은 Cascaded H-bridge 멀티레벨 인버터의 출력 전압 레벨 수의 증가를 위한 모델과 스위칭 기법을 제안한다. 제안하는 모델은 기존의 Cascaded H-bridge 멀티레벨 인버터 구조에서 각 H-bridge 모듈의 출력단에 변압기를 연결하고, 변압기 2차측을 직렬로 연결한 모델이다. 이 구조에서 다수의 변압기의 턴비는 동일하고, 1개의 변압기 턴비만이 다른 턴비를 갖게된다. 따라서 1개의 변압기 턴비를 조절하여 출력전압의 전압 레벨수를 증가시킬 수 있다. 스위칭 방법은 기존에 멀티레벨 인버터에서 주로 사용되는 Level-shifted PWM 방식을 이용하여 간단하게 구현할 수 있다. 제안하는 모델의 검증을 위하여 시뮬레이션을 수행하여 제안하는 모델의 타당성을 확인한다.

• Journal of Electrical Engineering and Technology
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• v.8 no.2
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• pp.316-325
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• 2013

Multilevel inverters produce a staircase output voltage from DC voltage sources. Requiring great number of semiconductor switches is main disadvantage of multilevel inverters. The multilevel inverters can be divided in two groups: symmetric and asymmetric converters. The asymmetric multilevel inverters provide a large number of output steps without increasing the number of DC voltage sources and components. In this paper, a novel topology for multilevel converters is proposed using cascaded sub-multilevel Cells. This sub-multilevel converters can produce five levels of voltage. Four algorithms for determining the DC voltage sources magnitudes have been presented. Finally, in order to verify the theoretical issues, simulation is presented.