• Korean Journal of Optics and Photonics
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• v.7 no.1
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• pp.66-71
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• 1996

We analyzed and fabricated InP/InGaAs avalanche photodiode (APD) having floating guard ring (FGR). Since the FGR-APD is very simple to fabricate and highly reliable, the fabrication of FGR-APD and its application to the optical receiver are very useful and interesting. A double zinc diffusion was employed to fabricate and one dimensional electric field analysis was used for design. Two dimensional gain measurement showed that the FGR suppressed gain at the curved edge, indicating the successful behavior as a guard ring. The fabricated device had 35 GHz of gain-bandwidth product, and showed the sensitivity of -31.9 dBm at a bit error rate of $10^{-9}$ when it was applied to a 2.5 Gbps optical receiver.

• Proceedings of the Materials Research Society of Korea Conference
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• 2006.11a
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• pp.19.1-19.1
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• 2006

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.161-164
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• 2002

This paper presents an 1-D substrate resistance value expression and compares the measured wave-form data with the calculated 1-D resistance network model. The remaining part is devoted to the effectiveness of guard ring varying its width and number.

• Journal of the Korean Society of Marine Environment & Safety
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• v.14 no.2
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• pp.157-162
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• 2008

The ship's maneuverability is the important factor to avoid ship's collisions. The ship's maneuverability is usually measured in a deep water, and the turning ability is decreased and the course stability is improved in a shallow water. The variation of the turning ability could cause the risk of collision. In this paper, we proposes application technique of Variable Safe-Guard Ring to consider the shallow water effect and to be simple to estimate the grade of collision risk simultaneously. Through the mathematical simulation, the availability of new method was varified. Therefore this method is expected enough to support a maneuver for collision avoidance.

• Proceedings of the KIEE Conference
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• 2001.11a
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• pp.26-28
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• 2001

A Trench schottky diode with guard ring is proposed to improve the forward current density and reverse breakdown voltage. The simulation results by Silvaco have shown that the reverse breakdown voltage of the proposed device was found to be 22.1V while that of conventional trench device was 17.25V. The breakdown voltage of the proposed structure was 28.1% higher than that of the conventional trench structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1603-1610
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• 1999

본 논문은 CMOS의 latch-up 특성을 개선하기 위한 효과적인 mask 설계 방법에 관한 것이다. Mask의 평면구조와 latch-up 파라메타와의 상관관계를 실물 제작에 의한 실험과 컴퓨터 시뮬레이션에 의해 도출하였으며, guard ring의 효과에 대해서도 비교 분석하였다. 실험 결과, 수평구조 바이폴라 트랜지스터의 전류증폭률($\beta$n)이 디자인룰에 반비례하였으며, 수직구조 바이폴라 트랜지스터의 전류증폭률($\beta$n)은 디지인룰과 무관하였다. 스위칭전압과 유지전류는 디자인룰에 비례하였다. Guard ring은 latch-up의 가능성을 줄이는 데 상당한 효과가 있었음이 확인되었으며, Guard ring이 없는 경우에 비하여 전류증폭률의 곱($\beta$n$\beta$n)이 약 31% 감소, 유지전류는 약 25%가 향상됨을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.105-112
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• 2009

In this paper, we investigated abnormal ESD failure on guard-rings in the smart power IC fabricated with $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology. Initially, ESD failure occurred below 200 V in the Machine Model (MM) test due to current crowding in the parasitic diode associated with the guard-rings which are generally adopted to prevent latch-up in high voltage devices. Optical Beam Induced Resistance Charge (OBIRCH) and Scanning Electronic Microscope (SEM) were used to find the failure spot and 3-D TCAD was used to verify cause of failure. According to the simulation results, excessive current flows at the comer of the guard-ring isolated by Local Oxidation of Silicon (LOCOS) in the ESD event. Eventually, the ESD failure occurs at that comer of the guard-ring. The modified comer design of the guard-ring is proposed to resolve such ESD failure. The test chips designed by the proposed modification passed MM test over 200 V. Analyzing the test chips statistically, ESD immunity was increased over 20 % in MM mode test. In order to avoid such ESD failure, the automatic method to check the weak point in the guard-ring is also proposed by modifying the Design Rule Check (DRC) used in BCD technology. This DRC was used to check other similar products and 24 errors were found. After correcting the errors, the measured ESD level fulfilled the general industry specification such as HBM 2000 V and MM 200V.

• Proceedings of the Materials Research Society of Korea Conference
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• 2007.05a
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• pp.22.1-22.1
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• 2007

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.86-89
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• 2007

실리콘을 사용한 X선 감지 용 센서 어레이 제작에 대해 연구하였다. 단일 센서 소자에서는 필수적인 guard ring구조가 어레이에서는 적절히 설계되지 못할 경우 누설전류 증가를 초래하는 것으로 나타났다. 즉, 누설전류는 공??????층 두께와 능동영역 및 guard ring 구조 간 거리에 매우 민감한 것으로 조사되었다. 또한 다결정 실리콘과 n형 도핑 소스로 인을 활용하는 조합이 결함 gettering을 위한 효율적인 방법임이 입증되었으나 고온 공정과정에 보호되지 않은 채 노출되는 경우에는 효과적이지 못한 것으로 관측되었다. 본 연구에서는 이러한 결과들을 고려하여 어레이를 제작하였으며 우수한 특성을 관찰할 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.8
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• pp.898-907
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• 1992

This paper deals with a detailed analysis of CMOS latch up dependancies on the layout and geo-metrical demensions on the mask using same materials and same processes. For this purpose, six different layout models depending upon the N+ / P+ spacing and three different guard ring models have been gesigned, fabricated, and tested. As a result, common emitter current gain, shunt resistance, and holeing current versus N+/P+ spacing have been measured and analyzed experimentally. Also the fact that guard ring is sffective in reducing the latchup possibility has been verified through this study.