• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.277-282
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• 2017

Nickel germanide (NiGe) is one of the most promising alloy materials for source/drain (S/D) of Ge MOSFETs. However, NiGe has limited thermal stability up to $450^{\circ}C$ which is a challenge for fabrication of Ge MOSFETs. In this paper, a novel method is proposed to improve the thermal stability of NiGe using Co interlayer. As a result, we found that the thermal stability of NiGe was improved from $450^{\circ}C$ to $570^{\circ}C$ by using the proposed Co interlayer. Furthermore, we found that current-voltage (I-V) characteristic was improved a little by using Co/Ni/TiN structure after post-annealing. Therefore, NiGe formed by the proposed Co interlayer that is, Co/Ni/TiN structure, is a promising technology for S/D contact of Ge MOSFETs.

• ETRI Journal
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• v.27 no.4
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• pp.439-445
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• 2005

We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility $Si_{0.8}Ge_{0.2}$ buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 ${\mu}m$) $Si_xGe_{1-x}$ relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) $Si_{0.8}Ge_{0.2}$ layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.101-102
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• 2009

SGOI MOSFETs with various Ge mole fractions were fabricated and compared to the SOI MOSFET. SGOI MOSFETs have a lager drain current and higher effective mobility than the SOI MOSFET as increased Ge mole fractions. The lattice constant difference causes lattice mismatch between the SiGe layer and the top-Si layer during the top-Si layer growth. However, SGOI MOSFETs have a lager leakage current at subthreshold region. Also, leakage current at subthreshold region increased with Ge mole fractions. This is attributable to the crystalline defects due to the lattice mismatch between the SiGe layer and the top-Si layer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.210-214
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• 2016

In this paper, the decrease in the contact resistance of Ni germanide/Ge contact was studied as a function of the thickness of the antimony (Sb) interlayer for high performance Ge MOSFETs. Sb layers with various thickness of 2, 5, 8 and 12 nm were deposited by RF-Magnetron sputter on n-type Ge on Si wafers, followed by in situ deposition of 15nm-thick Ni film. The contact resistance of samples with the Sb interlayer was lower than that of the reference sample without the Sb interlayer. We found that the Sb interlayer can lower the contact resistance of Ni germanide/Ge contact but the reduction of contact resistance becomes saturated as the Sb interlayer thickness increases. The proposed method is useful for high performance n-channel Ge MOSFETs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.733-737
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• 2008

In this paper, Ni-Co alloy was used to improve thermal stability of Ni Germanide. It was found that uniform germanide is obtained on epitaxial Ge-on-Si substrate by employing Ni-Co alloy. Moreover, neither agglomeration nor penetration is observed during post-germanidation annealing process. The thermal stability of Ni germanide using Ni-Co alloy is improved due to the less agglomeration of Germanide. Therefore, the proposed Ni-Co alloy is promising for highly thermal immune Ni germanide for nano scale Ge-MOSFETs technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.150-151
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• 2006

$Si_{0.88}Ge_{0.12}$/Si heterostructure channels grown by RPCVD were employed to n-type metal oxide semiconductor field effect transistors(MOSFETs), and their electrical properties were investigated. SiGe nMOSFETs presented very high transconductance compared to conventional Si-bulk MOSFETs, regardless substantial drawbacks remaining in subthreshold-slope, $I_{off}$, and leakage current level. It looks worthwhile to utilize excellent transconductance properties into rf applications requesting high speed and amplification capability, although optimization works on both device structure and unit processes are necessary for enhanced isolation and reduced power dissipation.

• ETRI Journal
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• v.25 no.3
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• pp.203-209
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• 2003

This paper reports on our investigation of DC and RF characteristics of p-channel metal oxide semiconductor field effect transistors (pMOSFETs) with a compressively strained $Si_{0.8}Ge_{0.2}$ channel. Because of enhanced hole mobility in the $Si_{0.8}Ge_{0.2}$ buried layer, the $Si_{0.8}Ge_{0.2}$ pMOSFET showed improved DC and RF characteristics. We demonstrate that the 1/f noise in the $Si_{0.8}Ge_{0.2}$ pMOSFET was much lower than that in the all-Si counterpart, regardless of gate-oxide degradation by electrical stress. These results suggest that the $Si_{0.8}Ge_{0.2}$ pMOSFET is suitable for RF applications that require high speed and low 1/f noise.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.6
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• pp.491-495
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• 2007

This paper has demonstrated the electrical properties of SiGe pMOSFETs fabricated on both bulk-Si and PD SOI substrates. Two principal merits, the mobility increase in strained-SiGe channel and the parasitic capacitance reduction of SOI isolation, resulted in improvements in device performance. It was observed that the SiGe PD SOI could alleviate the floating body effect, and consequently DIBL was as low as 10 mV/V. The cut-off frequency of device fabricated on PD SOI substrate was roughly doubled in comparison with SiGe bulk: from 6.7 GHz to 11.3 GHz. These experimental result suggests that the SiGe PD SOI pMOSFET is a promising option to drive CMOS to enhance performance with its increased operation frequency for high speed and low noise applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.4
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• pp.271-275
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• 2011

In this paper, thermal stability of palladium germanide (Pd germanide) is analyzed for high performance Schottky barrier germanium metal oxide semiconductor field effect transistors (SB Ge-MOSFETs). Pd germanide Schottky barrier diodes were fabricated on n-type Ge-on-Si substrates and the formed Pd germanide shows thermal immunity up to $450^{\circ}C$. The barrier height of Pd germanide is also characterized using two methods. It is shown that Pd germanide contact has electron Schottky barrier height of 0.569~0.631 eV and work function of 4.699~4.761 eV, respectively. Pd germanide is promising for the nanoscale Schottky barrier Ge channel MOSFETs.