• 한국전기전자재료학회논문지
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• 제21권1호
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• pp.44-48
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• 2008

Hole mobility characteristics of two representative biaxially strained SiGe/Si structures with high Ge contents are studied, They are single channel ($Si/Si_{1-x}Ge_x/Si$ substrate) and dual channel ($Si/Si_{1-y}Ge_y/Si_{1-x}Ge_x/Si$ substrate), where the former consists of a relaxed SiGe buffer layer with 60 % Ge content and a tensile-strained Si layer on top, and for the latter, a compressively strained SiGe layer is inserted between two layers, Owing to the hole mobility performance between a relaxed SiGe film and a compressive-strained SiGe film in the single channel and the dual channel, the hole mobility behaviors of two structures with respect to the Si cap layer thickness shows the opposite trend, Hole mobility increases with thicker Si cap layer for single channel structure, whereas it decreases with thicker Si cap layer for dual channel. This hole mobility characteristics could be easily explained by a simple capacitance model.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.113-114
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• 2007

Hole mobility characteristics of single surface channel and dual channel Si/SiGe structure are compared, where the former one consists of a relaxed SiGe buffer layer and a tensile strained Si layer on top, and for dual channel structure a compressively strained SiGe layer is inserted between them. Due to the difference of hole mobility enhancement factors of layers between them, hole mobility characteristics with respect to the Si cap thickness shows the opposite tend. Hole mobility increases with thicker Si cap for single channel structure, whereas it decreases with thicker Si cap for dual channel structure.

• ETRI Journal
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• 제41권6호
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• pp.829-837
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• 2019

The p-type nanowire field-effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in-depth technology computer-aided design (TCAD) with quantum models for sub-10-nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence-band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L_g) by examining a set of primary DC and AC parameters. The cutoff frequency (f_T) and maximum oscillation frequency (f_max) of the proposed device were determined to be 440.0 and 753.9 GHz when L_g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe-shell channel p-type nanowire FET has demonstrated a strong potential for low-power and high-speed applications in 10-nm-and-beyond complementary metal-oxide-semiconductor (CMOS) technology.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.541-544
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• 1998

A SiGe p-channel MESFET using $\delta-doped$ layers is designed and the considerable enhancement of the current driving capability of the device is observed from the result of simulation. The channel consists of double $\delta-doped$ layers separated by a low-doped spacer which consists of Si and SiGe. A quantum well is formed in the valence band of the Si/SiGe heterojunction and much more holes are accumulated in the SiGe spacer than those in the Si spacer. The saturation current is enhanced by the contribution of the holes inthe spacer. Among the design parameters that affect the performance of the device, the thickness of the SiGe layer and the Ge composition are studied. The thickness of $0~300\AA$ and the Ge composition of 0~30% are investigated, and the saturation current is observed to be increased by 45% compared with a double $\delta-doped$ Si p-channel MESFET.

• 한국전기전자재료학회논문지
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• 제22권11호
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• pp.905-909
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• 2009

The new Junction Field Effect Transistors (JFETs) with Silicon-germanium (SiGe) layers is investigated. This structure uses SiGe layer to prevent out diffusion of boron in the channel region. In this paper, we report electrical properties of SiGe JFET measured under various design parameters influencing the performance of the device. Simulation results show that out diffusion of boron is reduced by the insertion SiGe layers. Because the SiGe layer acts as a barrier to prevent the spread of boron. This proposed JFET, regardless of changes in fabrication processes, accurate and stable cutoff voltage can be controlled. It is easy to maintain certain electrical characteristics to improve the yield of JFET devices.

• ETRI Journal
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• 제27권4호
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• pp.439-445
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• 2005

We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility $Si_{0.8}Ge_{0.2}$ buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 ${\mu}m$) $Si_xGe_{1-x}$ relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) $Si_{0.8}Ge_{0.2}$ layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.106-113
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• 2006

Electrical properties of $Si_{0.88}Ge_{0.12}(C)$ p-MOSFETs have been exploited in an effort to investigate $Si_{0.88}Ge_{0.12}(C)$ channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in $Si_{0.88}Ge_{0.12}$ channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide. $Si_{0.88}Ge_{0.12}(C)$ channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of $Si_{0.88}Ge_{0.12}(C)$ heterostructures.

• 전자공학회논문지D
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• 제36D권4호
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• pp.86-92
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• 1999

SiGe을 이용한 p형 전계 효과 트랜지스터의 전류 구동 능력 향상을 위하여 이중 δ도핑층을 이용한 MESFET을 설계하고 시뮬레이션을 통하여 전기적 특성의 개선을 확인하였다. 두 δ도핑층 사이의 도핑 농도가 낮은 분리층에 SiGe층을 위치시키면 양자 우물이 형성되어 δ도핑층에서 넘쳐 나온 정공이 Si 채널의 경우보다 더 많아져 전류 구동 능력이 크게 향상된다. δ도핑층 사이의 SiGe층의 두께는 0∼300Å, Ge 구성비는 0∼30%의 범위에서 변화시켜 SiGe 두께 200Å, Ge 구성비 30%일 때 이중 δ도핑 Si 채널 MESFET에 비해 최대 45% 이상 개선될 수 있음을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.847-853
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• 2016

Applications of Si have been increasingly exploited and extended to More-Moore, More-than-Moore, and beyond-CMOS approaches. Ge is regarded as one of the supplements for Si owing to its higher carrier mobilities and peculiar band structure, facilitating both advanced and optical applications. As an emerging metal-oxide device, the junctionless field-effect transistor (JLFET) has drawn considerable attention because of its simple process, less performance fluctuation, and stronger immunity against short-channel effects due to the absence of anisotype junctions. In this study, we investigated lateral field scalability, which is equivalent to channel-length scaling, in Si and Ge JLFETs. Through this, we can determine the usability of Si CMOS and hypothesize its replacement by Ge. For simulations with high accuracy, we performed rigorous modeling for ${\mu}_n$ and ${\mu}_p$ of Ge, which has seldom been reported. Although Ge has much higher ${\mu}_n$ and ${\mu}_p$ than Si, its saturation velocity ($v_{sat}$) is a more determining factor for maximum $I_{on}$. Thus, there is still room for pushing More-Moore technology because Si and Ge have a slight difference in $v_{sat}$. We compared both p- and n-type JLFETs in terms of $I_{on}$, $I_{off}$, $I_{on}/I_{off}$, and swing with the same channel doping and channel length/thickness. $I_{on}/I_{off}$ is inherently low for Ge but is invariant with $V_{DS}$. It is estimated that More-Moore approach can be further driven if Si is mounted on a JLFET until Ge has a strong possibility to replace Si for both p- and n-type devices for ultra-low-power applications.

• 한국진공학회지
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• 제15권1호
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• pp.31-36
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• 2006

[ $Li/Ge(111)-3{\times}1$ ] 표면의 구조를 고찰하기 위해, Ge 3d core-level 광전자 스펙트럼을 분석하였다. Curve fitting을 통하여 스펙트럼에서 bulk Ge 3d peak에 해당하는 peak의 양쪽에 각각 하나씩의 표면 성분이 있음을 확인하였다. $Li/Ge(111)-3\times1$ 표면의 core-level spectrum에서의 두 표면 peak의 존재와 그 위치는 같은 금속에 의해 유도된 $Si/Ge(111)-3\times1$의 경우와 유사하며, 이는 두 표면의 구조fl서의 유사성을 시사한다. $Li/Ge(111)-3\times1$ 표면의 core-level 광전자 스펙트럼에서 보이는 두 개의 표면 성분의 존재와 위치는 알칼리 금속으로부터 유도되는 $Si/Ge(111)-3\times1$의 구조 모형으로 제안된 honeycomb-chain 모형과 잘 일치한다.