• 한국전기전자재료학회논문지
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• 제13권11호
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• pp.895-900
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• 2000

In this paper, C-V characteristics based on the structure of GaAs MESFET’s has been proposed with wide range of applied voltages and temperatures. Small signal capacitance; gate-source and gate-drain capacitances are represented by analytical expressions which are classified into two different regions; linear and saturation regions with bias voltages. The expression contains two variables; the built-in voltage( $V_{vi}$ )and the depletion width(W). Submicron gate length MESFETs has been selected to prove the validity of the theoretical perdiction and shows good agreement with the experimental data over the wide range of applied voltages.

• 한국전자파학회논문지
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• 제10권5호
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• pp.663-671
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• 1999

본 연구에서는 GaAs MESFET의 게이트-소오스 캐패시턴스($C_{gs}$)와 드레인-소오스 전류($I_{ds}$)의 비션형성에 의한 이득감소(Gain Compression) 및 위상왜곡(Phase Distortion)특성을 알아보고, 이를 최소화 할 수 있 는 소오스 및 부하 임피던스의 조건에 대해 조사하였다. 먼저 Volterra - Series 분석을 통하여, $C_{gs}(V_{gs})$와 $I_{ds}(V_{gs})$의 비선형특성을 조사하고, 각각의 비선형성분이 상호 소멸되는 소오스 및 부하 임피던스의 조건에서, 전체소자의 비선형성이 최소화 됨을 얄아보았다. 그리고 소오스 및 부하측정(Source, Load Pull)을 통하여 출 력전력값에 따라 최적의 선형성이 나오는 입출력 임피던스값을 찾고, Volterra-Series에서 구한 이론적인 결과와 비교 및 분석을 행하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.550-553
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• 2001

In this study, unity current gain frequency f$\_$T/ of GaAs MESFET is predicted with different temperatures up to 400 $^{\circ}C$. Temperature dependence parameters of the device including intrinsic carrier concentration n$\_$i/ effective mass, depletion width are considered to be temperature dependent. Small signal parameters such as gate-source, gate dran capacitances C$\_$gs/ C$\_$gd/ are correlated with transconductance g$\_$m/ to predict the unity current gain frequency. The extrinsic capacitance which plays an important roles in high frequency region has been taken into consideration in evaluating total capacitance by using elliptic integral through the substrate. From the results, f$\_$T/ decreases as the temperature increases due to the increase of small signal capacitances and the mobility degradation. Finally the extrinsic elements of capacitances have been proved to be critical in deciding f$\_$T/ which are originated from the design rule of the device.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.312-317
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• 2015

In this paper, the RF characteristics of multi-finger MOSFETs were improved by decreasing the parasitic capacitance in spite of increased gate resistance in a 90-nm CMOS technology. Two types of device structures were designed to compare the parasitic capacitance in the gate-to-source ($C_{gs}$) and gate-to-drain ($C_{gd}$) configurations. The radio frequency (RF) performance of multi-finger MOSFETs, such as cut-off frequency ($f_T$) and maximum-oscillation frequency ($f_{max}$) improved by approximately 10% by reducing the parasitic capacitance about 8.2% while maintaining the DC performance.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권3호
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• pp.196-208
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• 2007

An analytical model is proposed for an optically controlled Metal Semiconductor Field Effect Transistor (MESFET), known as Optical Field Effect Transistor (OPFET) considering the diffusion fabrication process. The electrical parameters such as threshold voltage, drain-source current, gate capacitances and switching response have been determined for the dark and various illuminated conditions. The Photovoltaic effect due to photogenerated carriers under illumination is shown to modulate the channel cross-section, which in turn significantly changes the threshold voltage, drainsource current, the gate capacitances and the device switching speed. The threshold voltage $V_T$ is reduced under optical illumination condition, which leads the device to change the device property from enhancement mode to depletion mode depending on photon impurity flux density. The resulting I-V characteristics show that the drain-source current IDS for different gate-source voltage $V_{gs}$ is significantly increased with optical illumination for photon flux densities of ${\Phi}=10^{15}\;and\;10^{17}/cm^2s$ compared to the dark condition. Further more, the drain-source current as a function of drain-source voltage $V_{DS}$ is evaluated to find the I-V characteristics for various pinch-off voltages $V_P$ for optimization of impurity flux density $Q_{Diff}$ by diffusion process. The resulting I-V characteristics also show that the diffusion process introduces less process-induced damage compared to ion implantation, which suffers from current reduction due to a large number of defects introduced by the ion implantation process. Further the results show significant increase in gate-source capacitance $C_{gs}$ and gate-drain capacitance $C_{gd}$ for optical illuminations, where the photo-induced voltage has a significant role on gate capacitances. The switching time ${\tau}$ of the OPFET device is computed for dark and illumination conditions. The switching time ${\tau}$ is greatly reduced by optical illumination and is also a function of device active layer thickness and corresponding impurity flux density $Q_{Diff}$. Thus it is shown that the diffusion process shows great potential for improvement of optoelectronic devices in quantum efficiency and other performance areas.

• Journal of electromagnetic engineering and science
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• 제14권2호
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• pp.68-73
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• 2014

A linear stacked field-effect transistor (FET) power amplifier (PA) is implemented using a $0.18-{\mu}m$ silicon-on-insulator CMOS process for W-CDMA handset applications. Phase distortion by the nonlinear gate-source capacitance ($C_{gs}$) of the common-source transistor, which is one of the major nonlinear sources for intermodulation distortion, is compensated by employing a PMOS linearizer with improved AM-PM. The linearizer is used at the gate of the driver-stage instead of main-stage transistor, thereby avoiding excessive capacitance loading while compensating the AM-PM distortions of both stages. The fabricated 836.5 MHz linear PA module shows an adjacent channel leakage ratio better than -40 dBc up to the rated linear output power of 27.1 dBm, and power-added efficiency of 45.6% at 27.1 dBm without digital pre-distortion.

• Journal of Electrical Engineering and Technology
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• 제11권6호
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• pp.1763-1768
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• 2016

This paper presents the electrical characteristics of the gallium nitride (GaN) current aperture vertical electron transistor (CAVET) by using two-dimensional (2-D) technology computer-aided design (TCAD) simulations. The CAVETs are considered as the alternative device due to their high breakdown voltage and high integration density in the high-power applications. The optimized design for the CAVET focused on the electrical performances according to the different gate-source length ($L_{GS}$) and aperture length ($L_{AP}$). We analyze DC and RF parameters inducing on-state current ($I_{on}$), threshold voltage ($V_t$), breakdown voltage ($V_B$), transconductance ($g_m$), gate capacitance ($C_{gg}$), cut-off frequency ($f_T$), and maximum oscillation frequency ($f_{max}$).