• The Journal of the Acoustical Society of Korea
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• v.39 no.5
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• pp.414-423
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• 2020

In this paper, we propose a Dilated Convolution Gate Linear Unit (DCGLU) to mitigate the lack of sparsity and small receptive field problems caused by the segmentation map extraction process in sound event detection with weak labels. In the advent of deep learning framework, segmentation map extraction approaches have shown improved performance in noisy environments. However, these methods are forced to maintain the size of the feature map to extract the segmentation map as the model would be constructed without a pooling operation. As a result, the performance of these methods is deteriorated with a lack of sparsity and a small receptive field. To mitigate these problems, we utilize GLU to control the flow of information and Dilated Convolutional Neural Networks (DCNNs) to increase the receptive field without additional learning parameters. For the performance evaluation, we employ a URBAN-SED and self-organized bird sound dataset. The relevant experiments show that our proposed DCGLU model outperforms over other baselines. In particular, our method is shown to exhibit robustness against nature sound noises with three Signal to Noise Ratio (SNR) levels (20 dB, 10 dB and 0 dB).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.47-52
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• 2006

This paper proposes a novel low-power $32bit\times32bit$ multiplier for deep submicron technologies beyond 130nm. As technology becomes small, static power due to leakage current significantly increases, and it becomes comparable to dynamic power. Recently, shutdown method based on MTCMOS is widely used to reduce both dynamic and static power. However, it suffers from severe power line noise when restoring whole large-size functional block. Therefore, the proposed multiplier mitigates this noise by shutting down and waking up sequentially along with pipeline stage. Fabricated chip measurement results in $0.35{\mu}m$ technology and gate-transition-level simulation results in 130nm and 90nm technologies show that it consumes $66{\mu}W,\;13{\mu}W,\;and\;6{\mu}W$ in idle mode, respectively, and it reduces power consumption to $0.04%\sim0.08%$ of active mode. As technology becomes small, power reduction efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Journal of IKEEE
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• v.19 no.4
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• pp.596-602
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• 2015

In this paper, a unified inverse transformer is designed for HEVC and VP9. The proposed architecture performs all modes of HEVC and VP9 in the unified inverser transformer, such as $4{\times}4{\sim}32{\times}32$ HEVC IDCT, $4{\times}4$ HEVC IDST, $4{\times}4{\sim}32{\times}32$ VP9 IDCT, $4{\times}4{\sim}16{\times}16$ VP9 IADST and $4{\times}4$ IWHT. Same computations are used in HEVC IDCT and VP9 IDCT, except for the scales of the coefficients. Similarly, same computations are used in HEVC $4{\times}4$ IDST and VP9 $4{\times}4$ IADST, except for the scales of the coefficients. Furthermore, HEVC IDCT, VP9 IDCT, and VP9 IADST are the subsets of upper level IDCTs. The proposed architecture reuses multipliers when the computation is identical. Also it shares adders and butterfly structures even when the multiplier coefficients are different. So it reduces the hardware size significantly. Synthesized in 0.18 um technology, the gate count is 456,442 gates. which achieved 22.6% reduction compared to conventional architectures.

• Journal of IKEEE
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• v.21 no.4
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• pp.388-396
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• 2017

Since there are many variables such as various poses, illuminations and occlusions in a face detection problem, a high performance detection system is required. Although CNN is excellent in image classification, CNN operatioin requires high-performance hardware resources. But low cost low power environments are essential for small and mobile systems. So in this paper, the CPU-FPGA integrated system is designed based on 3-stage cascade CNN architecture using small size FPGA. Adaptive Region of Interest (ROI) is applied to reduce the number of CNN operations using face information of the previous frame. We use a Field Programmable Gate Array(FPGA) to accelerate the CNN computations. The accelerator reads multiple featuremap at once on the FPGA and performs a Multiply-Accumulate (MAC) operation in parallel for convolution operation. The system is implemented on Altera Cyclone V FPGA in which ARM Cortex A-9 and on-chip SRAM are embedded. The system runs at 30FPS with HD resolution input images. The CPU-FPGA integrated system showed 8.5 times of the power efficiency compared to systems using CPU only.

• Korean Journal of Materials Research
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• v.8 no.10
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• pp.918-924
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• 1998

This study has been carried out to investigate the effect of reaction milling time on the synthesis of Ti- TiC p powder synthesised from the elemental titanium and activated carbon by reaction milling(RM), and the effect of vacu­u urn hot pressing temperature and TiC volume fraction on microstructural and mechanical properties of Ti- TiC com­p posite $\infty$ns이idated by vacuum hot pressing(VHP).T The elemental powders of titanium and activated carbon can be converted into Ti- TiC composite powders by reac­t tion milling for about 300hours, and were the average grain size of the as- milled powders has been measured to be a about $5\mu\textrm{m}$. The relative density of Ti- TiC VHPed above $1000^{\circ}C$ during Ihr is about 98% and the mechanical properties o of In- situ Ti- TiC composites are improved by TiC particle dispersed uniformly on titanium matrix. In order to investi­g gate thermal stability of Ti- TiC composite, after annealing at $600^{\circ}C$ for 80hrs micro- Vickers hardness have been per­f formed, and the values have been shown little changed as compared with those before annealing. The compact has b been tested on high temperature compressive test at $700^{\circ}C$ and has showed a high temperature compressive strength of 330MPa in a Ti- 20vol% TiC.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Journal of the Korean Vacuum Society
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• v.9 no.3
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• pp.258-262
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• 2000

$YMnO_3$thin films are deposited on Si(100) and $Y_2O_3/Si(100)$ substrate by radio frequency sputtering. The deposition condition of oxygen partial pressure and annealing temperature have significant influences on the preferred orientation of $YMnO_3$film and the size of memory window. The results of x-ray diffraction show that the film deposited in the oxygen partial pressure of 0% is highly oriented along c-axis after annealing at $870^{\circ}C$ for 1 hr in oxygen ambient. However, the films deposited on Si and $Y_2O_3/Si$ in the oxygen partial pressures of 20% show $Y_2O_3$ peak, the excess $Y_2O_3$ in the $YMnO_3$film suppresses the c-axis oriented crystallization. Especially memory windows of the $Pt/YMnO_3/Y_2O_3/Si$ capacitor are 0.67~3.65 V at applied voltage of 2~12 V, which is 3 times higher than that of the film deposited on $Y_2O_3/Si$ in 20% oxygen (0.19~1.21 V) at the same gate voltage because the film deposited in 0% oxygen is well crystallized along c-axis.

• Korean Journal of Heritage: History & Science
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• v.43 no.1
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• pp.212-235
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• 2010

The purpose of this study is to examine the characteristics of the location and the spatial composition of Uireung that is located in Seokgwan-dong, Seongbuk-gu, Seoul, in order to understand the landscape architectural characteristics. The results are as follows. First, Uireung is 6.4km from Changdeokgung Palace and 5.5km from Heunginjimun Gate. It did not violate the distance standard (40km) for the royal tombs according to Joseon Dynasty Neung-won Myo-je. Second, Uireung is in harmony with the nature and shows the authoritative characteristics of the royal authority through the spatial composition and rank(Entrance Area, Ceremonial Area, Burial Area). Third, there are burial mound, stone sheep, stone tiger, stone table, stone watch pillars in the upper platform, and stone civil official, stone horse, stone lantern in the middle platform, and stone military official, stone horse in the lower platform, and T-shape shrine, worship road in the ceremonial area. There is no pond and a tomb keeper residence, but the position, size, and form can be approximated through historical research materials. There are a colony of pine trees around the burial mound and 64 species of trees such as pine tree, zelcova tree, and fir tree below the burial mound.