• 제목/요약/키워드: Gate size

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Scaling theory to minimize the roll-off of threshold voltage for nano scale MOSFET (나노 구조 MOSFET의 문턱전압 변화를 최소화하기 위한 스케일링 이론)

  • 김영동;김재홍;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.11a
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    • pp.494-497
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    • 2002
  • In this paper, we have presented the simulation results about threshold voltage of nano scale lightly doped drain (LDD) MOSFET with halo doping profile. Device size is scaled down from 100nm to 40nm using generalized scaling. We have investigated the threshold voltage for constant field scaling and constant voltage scaling using the Van Dort Quantum Correction Model(QM) and direct tunneling current for each gate oxide thickness. We know that threshold voltage is decreasing in the constant field scaling and increasing in the constant voltage scaling when gate length is reducing, and direct tunneling current is increasing when gate oxide thickness is reducing. To minimize the roll-off characteristics for threshold voltage of MOSFET with decreasing channel length, we know u value must be nearly 1 in the generalized scaling.

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The Gateway for Internet Server Implementation using Dynamic IP Address (동적 IP Address를 사용하는 인터넷 서버 구축을 위한 게이트웨이)

  • Kim, Won-Jung;Yang, Hyeon-Taek
    • The KIPS Transactions:PartD
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    • v.9D no.1
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    • pp.145-152
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    • 2002
  • Recently most of the home and small-size company use ADSL(Asymmetric Digital subscriber Line) or Cable Modem for using Internet Services. The number of Internet IP Address in current Internet IP Address System(IPv4) that is consisted of 4byte is almost empty, so generally the IP Address assigned dynamically is used. This way is just OK in general uses, but not OK in Internet Servers operation. This paper designed the gateway(Gate-D) system which is enable any system that get IP Address assigned dynamically to serve Internet Server Services(Telnet, FTP, HTTP, Mail, etc …), and made sure the worth by using Telnet Server.

A Study on the DC parameter matching according to the shrink of 0.13㎛ technology (0.13㎛ 기술의 shrink에 따른 DC Parameter 매칭에 관한 연구)

  • Mun, Seong-Yeol;Kang, Seong-Jun;Joung, Yang-Hee
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.11
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    • pp.1227-1232
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    • 2014
  • This paper relates 10% shrink from $0.13{\mu}m$ design for core devices as well as input and output (I/O) devices different from previous poly length shrink size only. We analyzed body effect with different channel length and doping profile simulation. After fixing the gate oxide module process, LDD implant conditions were optimized such as decoupled plasma nitridation of gate oxide, TEOS oxide $100{\AA}$ before LDD implant and 22o tilt-angle(45o twist-angle) LDD implant respectively to match the spice DC parameters of pre-shrink and finally matched them within 5%.

High-Performance Metal-Substrate Power Module for Electrical Applications

  • Kim, Jongdae;Oh, Jimin;Yang, Yilsuk
    • ETRI Journal
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    • v.38 no.4
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    • pp.645-653
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    • 2016
  • This paper demonstrates the performance of a metal-substrate power module with multiple fabricated chips for a high current electrical application, and evaluates the proposed module using a 1.5-kW sinusoidal brushless direct current (BLDC) motor. Specifically, the power module has a hybrid structure employing a single-layer heat-sink extensible metal board (Al board). A fabricated motor driver IC and trench gate DMOSFET (TDMOSFET) are implemented on the Al board, and the proper heat-sink size was designed under the operating conditions. The fabricated motor driver IC mainly operates as a speed controller under various load conditions, and as a multi-phase gate driver using an N-ch silicon MOSFET high-side drive scheme. A fabricated power TDMOSFET is also included in the fabricated power module for three-phase inverter operation. Using this proposed module, a BLDC motor is operated and evaluated under various pulse load tests, and our module is compared with a commercial MOSFET module in terms of the system efficiency and input current.

Corrosion and Sliding Properties of the Nickel-Based Alloys for the Valve Seats Application

  • Honda, Tadashi
    • Corrosion Science and Technology
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    • v.7 no.2
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    • pp.92-98
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    • 2008
  • This paper describes the experiments of the corrosion and the sliding tests of the nickel-based alloys for the gate valve seating materials used at high pressure and temperature. The general corrosion rates and IGC susceptibility are tested in pressurized water at 533 K and 575 K and in Strauss test solution. The sliding tests have been done in pressurized water at 293 k, 473 K and 573 k. The alloys containing above 10% chromium may have the anti-corrosion properties that could be applied to the valve seats for the power plants. The good sliding performance and the good pressure tightness are obtained when the disc specimens that have hardness 500 to 600 Hv combined with the seat specimens that have hardness 250 to 410 Hv containing about 40 percent of iron. The large size gate valves sliding tests have certified the test results. The anti-wear properties of the seat alloy and the anti-IGC susceptibility of the disc alloy could be improved by the addition of silicon and niobium, respectively.

A Study on Injection Mold Design Using Approximation Optimization (근사 최적화 방법을 이용한 사출금형 설계에 관한 연구)

  • Byon, Sung-Kwang;Choi, Ha-Young
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.19 no.6
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    • pp.55-60
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    • 2020
  • The injection molding technique is a processing method widely used for the production of plastic parts. In this study, the gate position, gate size, packing time, and melt temperature were optimized to minimize both the stress and deformation that occur during the injection molding process of medical suction device components. We used a central composite design and Latin hypercube sampling to acquire the data and adopted the response surface method as an approximation method. The efficiency of the optimization of the injection molding problem was determined by comparing the results of a genetic algorithm, sequential quadratic programming, and a non-dominant classification genetic algorithm.

A Study on Doped Poly of 8" process for Trench Power MOSFET Application (8" Trench Power MOSFET 응용을 위한 Doped Poly 공정연구)

  • Yang, Chang-Heon;Kim, Gwon-Je;Kwon, Young-Soo;Shin, Hoon-Kyu
    • Proceedings of the KIEE Conference
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    • 2011.07a
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    • pp.1501-1502
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    • 2011
  • In this paper, an investigation of the 8" process for Trench Power MOSFET Application and Trench MOSFETs and its impact on device performance is presented. Layout dimensions of trench power MOSFETs have been continuously reduced in order to decrease the specific on-resistance, maintaining equal vertical dimensions. We discuss experimental results for devices with a pitch size down fabricated with an unconventional gate trench topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are observed the trench gate oxidation by SEM.

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Low Power Reliable Asynchronous Digital Circuit Design for Sensor System (센서 시스템을 위한 저전력 고신뢰의 비동기 디지털 회로 설계)

  • Ahn, Jihyuk;Kim, Kyung Ki
    • Journal of Sensor Science and Technology
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    • v.26 no.3
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    • pp.209-213
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    • 2017
  • The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of high area overhead and high power consumption. This paper proposes a new NCL gate based on power gating structure. The proposed $4{\times}4$ NCL multiplier based on power gating structure is compared to the conventional NCL $4{\times}4$ multiplier and MTNCL(Multi-Threshold NCL) $4{\times}4$ multiplier in terms of speed, power consumption, energy and size using PTM 45 nm technology.

Nanoscale NAND SONOS memory devices including a Seperated double-gate FinFET structure

  • Kim, Hyun-Joo;Kim, Kyeong-Rok;Kwack, Kae-Dal
    • Journal of Applied Reliability
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    • v.10 no.1
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    • pp.65-71
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    • 2010
  • NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

Microcode-based Output Pulse Generation for Remote Controller Application (원격조종장치를 위한 마이크로코드방식의 출력펄스발생회로)

  • 장현수;조경록;유영갑
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.18 no.10
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    • pp.1527-1536
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    • 1993
  • A new transmitter circuit for remote controllers is designed to provide flexibility and expandibility in function. The circuit employs a microcode approach to accept various code format, length and pulse widths through programming, and the precessing logics is eliminated to reduce its size. The circuit was Implemented using FPGA(Field Programmable Gate Array) and it was found to operate successfully).

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