• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.2
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• pp.74-79
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• 2018

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.3
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• pp.209-213
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• 2007

The MOS gate capacitance model presented here is determined by directly solving the coupled Poisson equations on the poly and silicon sides, and includes the polysilicon (poly) gate depletion effect. Our compact gate capacitance model exhibits an excellent fit with measured data and parameter values extracted from data are physically acceptable. The data are collected from 0.5, 0.35, 0.25 and $0.18{\mu}m$ CMOS technologies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.152-159
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• 2010

We propose a semi-analytical current conduction model for depletion-mode n-type nanowire field-effect transistors (NWFETs) with top-gate structure. The NWFET model is based on an equivalent circuit consisting of two back-to-back Schottky diodes for the metal-semiconductor (MS) contacts and the intrinsic top-gate NWFET. The intrinsic top-gate NWFET model is derived from the current conduction mechanisms due to bulk charges through the center neutral region as well as of accumulation charges through the surface accumulation region, based on the electrostatic method, and thus it includes all current conduction mechanisms of the NWFET operating at various top-gate bias conditions. Our previously developed Schottky diode model is used for the MS contacts. The newly developed model is integrated into ADS, in which the intrinsic part of the NWFET is developed by utilizing the Symbolically Defined Device (SDD) for an equation-based nonlinear model. The results simulated from the newly developed NWFET model reproduce considerably well the reported experimental results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.361-366
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• 2013

A full-range analytic drain current model for depletion-mode long-channel surrounding-gate nanowire field-effect transistor (SGNWFET) is proposed. The model is derived from the solution of the 1-D cylindrical Poisson equation which includes dopant and mobile charges, by using the Pao-Sah gradual channel approximation and the full-depletion approximation. The proposed model captures the phenomenon of the bulk conduction mechanism in all regions of device operation (subthreshold, linear, and saturation regions). It has been shown that the continuous model is in complete agreement with the numerical simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.10-17
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• 2009

Nano-Electro-Mechanical MOSFET (NEMFET) using Double-Gate MOSFET (DGMOS) structure can efficiently control the short channel effect. Espatially, subthreshold current of depletion-mode Double-Gate NEMFET (Dep-DGNEMFET) decreases in the off-state due to the thin equivalent-oxide thickness. Analytical $t_gap$ vs. $V_g$ equation for Dep-DGNEMFET is derived and characteristics for different device structures are analyzed. Dep-DGNEMFET structure is optimized to satisfy ITRS criteria.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.17-24
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• 2004

Quantum effects in the poly-gate are analyzed in two dimensions using the density-gradient method, and their impact on the short-channel effect of double-gate MOSFETs is investigated. The 2-D effects of quantum mechanical depletion at the gate to sidewall oxide is identified as the cause of large charge-dipole formation at the corner of the gate. The bias dependence of the charge dipole shows that the magnitude of the dipole peak-value increases in the subthreshold region and there is a large difference in carrier and potential distribution compared to the classical solution. Using evanescent-nude analysis, it is found that the quantum effect in the poly-gate substantially increases the short-channel effect and it is more significant than the quantum effect in the Si film. The penetration of potential contours into the poly-gate due to the dipole formation at the drain side of the gate corner is identified as the reason for the substantial increase in short-channel effects.

• Journal of the Korean Vacuum Society
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• v.1 no.3
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• pp.376-381
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• 1992

Tungsten silicide films were deposited on the highly phosphorus-doped poly Si/SiO2/Si substrates by Low Pressure Chemical Vapor Deposition. They were heat treated in different conditions. XTEM, SIMS and high frequency C-V analysis were conducted for characterization. It can be concluded that outdiffusion of phosphours impurity throught the silicide films lead to its depletion in the poly-Si gate region near the gate oxide, resulting in loss of capacitance and increase of effective gate oxide thickness.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.10
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• pp.665-671
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• 2017

Herein, we report the fabrication of low-voltage N-type organic field-effect transistors by using high capacitance fluorinated polymer gate dielectrics such as P(VDF-TrFE), P(VDF-TrFE-CTFE), and P(VDF-TrFE-CFE). Electron-withdrawing functional groups in PVDF-based polymers typically cause the depletion of negative charge carriers and a high contact resistance in N-channel organic semiconductors. Therefore, we incorporated intermediate layers of a low-k polymerto prevent the formation of a direct interface between PVDF-based gate insulators and the semiconducting active layer. Consequently, electron depletion is inhibited, and the high charge resistance between the semiconductor and source/drain electrodes is remarkably improved by the in corporation of solution-processed charge injection layers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.49-56
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• 2008

This paper introduces a compact analytical current conduction model of long-channel depletion-mode n-type nanowire field-effect transistors (NWFETs). The NWFET used in this work was fabricated with the bottom-up process and it has a bottom-gate structure. The model includes all current conduction mechanisms of the NWFET operating at various bias conditions. The results simulated from the newly developed NWFET model reproduce a reported experimental results within a 10% error.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.197-197
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• 1999

Gate oxide 의 두께 감소는 gate의 캐패시턴스를 증가시켜 트랜지스터의 속도를 빠르게 하며, 동시에 저전압 동작을 가능하게 하기 때문에 gate oxide 두께는 MOS 공정 세대가 진행되어감에 따라 계속 감소할 것이다. 이러한 얇은 산화막은 device design에 명시된 두께의 특성을 나타내야 한다. Gate oxide의 두께가 작아질수록 gate oxide와 crystalline silicon간의 계면효과가 박막의 두께의 결정에 심각한 영향을 주기 때문에 정확한 두께 계측이 어렵다. 이러한 영향과 계측방법에 따라서 두께 계측의 차이가 나타난다. XTEM은 사용한 parameter에, Ellipsometer는 refractive index에, MEIS(Medium) Energy Ion Scattering)은 에너지 분해능에, Capacitor-Voltage 측정은 depletion effect에 의해 영향을 받는다. 우리는 계면의 원자분해능 분석에 통상 사용되어온 High Resolution TEM을 이용하여 약 30~70$\AA$ SiO2층의 두께와 계면 구조에 대한 분석을 하여 이를 MEIS와 0.015nm의 고감도를 가진 SE(Spectroscopy Ellipsometer), C-V 측정 결과와 비교하여 가장 좋은 두께 계측 방법을 찾고자 한다.