• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1771-1777
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• 2016

In this thesis, the breakdown voltage characteristics of silicon nanowire N-channel GAA MOSFETs were analyzed through experiments and 3-dimensional device simulation. GAA MOSFETs with the gate length of 250nm, the gate dielectrics thickness of 6nm and the channel width ranged from 400nm to 3.2um were used. The breakdown voltage was decreased with increasing gate voltage but it was increased at high gate voltage. The decrease of breakdown voltage with increasing channel width is believed due to the increased current gain of parasitic transistor, which was resulted from the increased potential in channel center through floating body effects. When the positive charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was decreased due to the increased potential in channel center. When the negative charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was increased due to the decreased potential in channel center. We confirmed that the measurement results were agreed with the device simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.117-123
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• 2004

A 30 nm $In_{0.7}GaAs$ High Electron Mobility Transistor (HEMT) with triple-gate has been successfully fabricated using the $SiO_2/SiN_x$ sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance ($R_g$), the etchedback BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width ($W_g$) of 2x100m. The fabricated 30nm $In_{0.7}GaAs$ HEMTs showed $V_{th}$of -0.4V, $G_{m,max}$ of 1.7S/mm, and $f_T$ of 421GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50nm InGaAs HEMTs if the initial line length can be reduced to below 50nm order.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2851-2854
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• 2003

The purpose of this paper was to find out the stabilized and effective value of RC-parameter by using PSpice simulation, considering that gate signal voltage can be distorted by RC-delay of signal line. the results of this study were as follows: TFT-LCD with high quality resolution increased the number of gate signal line and this made TFT on-time shorter over-width of signal line to improve the performance of TFT made the electrostatic capacity increase and the time constant higher, making problems and errors. and owing to the decrease of the aperture ratio, an electro optic character of LCD, we must consider the capacity and the condition of production process in deciding the width and the thickness of the gate signal line.

• Journal of Power Electronics
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• v.18 no.2
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• pp.604-614
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• 2018

This paper proposes a synchronous switching technique for a Vienna rectifier that uses carrier-based pulse width modulation (CB-PWM). A three-phase Vienna rectifier, similar to a three-level T-type converter with three back-to-back switches, is used as a PWM rectifier. Conventional CB-PWM requires six independent gate signals to operate back-to-back switches. When internal switches are operated synchronously, only three independent gate signals are required, which simplifies the construction of gate driver circuits. However, with this method, total harmonic distortion of the input current is higher than that with conventional CB-PWM switching. A reactive current injection technique is proposed to improve current distortion. The performance of the proposed synchronous switching method and the effectiveness of the reactive current injection technique are verified using simulations and experiments performed with a set of Vienna rectifiers rated at 5 kW.

• Journal of The Korean Society of Agricultural Engineers
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• v.53 no.3
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• pp.35-41
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• 2011

A model test is carried out to investigate the vibration of truss type lift gate in the four major rivers project. The gate model scaled with the ratio of 1 : 25 is made of acryl panel dimensioned 1.6 m in width, 0.28 m in height in the concrete test flume. Firstly natural frequencies of the model gate are measured and the results are compared with the numerical results in order to verify the model. The amplitudes of the vibration are measured under the different gate opening and water level conditions. The results are analyzed to study the characteristics of the gate vibration according to the small gate opening, the large gate opening and the overflow conditions. These test results presents a basic data for the guide manuals of gate management and a design method to reduce the gate vibration of truss type lift gate. Finally, the vibration of truss type lift gate are assessed in comparison with those of formerly tainter gate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.260-264
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• 2017

Process variation effect on arch-structured gate stacked array (GSTAR) 3-D NAND flash is investigated. In case of arch-structured GSTAR, a shape of the arch channel is depending on an alignment of photo-lithography. Channel width fluctuates according to the channel hole alignment. When a shape of channel exceeds semicircle, channel width becomes longer, increasing drain current. However, electric field concentration on tunnel oxide decreases because less electric flux converges into a larger surface of tunnel oxide. Therefore, program efficiency is dependent on the process variation. Meanwhile, a radius of channel holes near the bottom side become smaller due to an etch slope. It also affects program efficiency as well as channel width. Larger hole radius has an advantage of higher drain current, but causes degradation of program speed.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2079-2088
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• 2014

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.439-442
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• 1990

GaAs MESFETs with the submicron gat are fabricated. $G_{m,mas}$ = 195mS/mm with the $0.5{\mu}m$ gate length and $G_{m,mas}$ = 170mS/mm with the $0.6{\mu}m$ gate lenth. $f_{mas}$ = 7GHz with the $1.5{\mu}m$ gate length and the $120{\mu}m$ gate width. We can estimate that $f_{mas}$ = 15GHz with $0.6{\mu}m$ gate length and that $f_{mas}$ = 18 ${\sim}$ 20GHz with the $0.5{\mu}m$ gate length.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1333-1335
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• 2000

In order to turn on the SCR gate, trigger signal source have to provide appropriate gate current and voltage under the gate rating based on the characteristic of SCR, the nature of load and power. It will be essential design factors such as trigger source impedance, trigger signal occurring, signal time width and turn off conditions. Also minimum gate trigger current is changed with the deterioration of SCR. SCR, which is needed large gate trigger current absolutely, is very important for SCR characteristic test because it causes unstable output in the misfile or makes a trouble to pulse trigger circuits. This paper shows scheme to test the performance of SCR with the precision analyzing mechanism and the changing trend of minimum gate current under the trigger conditions.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.9
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• pp.523-526
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• 2000

A dual gate trench emitter IGBT structure is proposed and studied numerically using the device simulator MEDICI. The on-state forward voltage drop latch-up current density turn-off time and breakdown voltage of the proposed structure are compared with those of the conventional DMOS-IGBT and trench gate IGBT structures. The proposed structure forms an additional channel and increases collector current level resulting in reduction of on -state forward voltage drop. In addition the trench emitter increases latch-up current density by 148% in comparison with that for the conventional DMOS-IGBT and by 83% compared with that for the trench gate IGBT without degradation in breakdown voltage when the half trench gate width(Tgw) and trench emitter depth(Ted) are fixed at $1.5\mum\; and\; 2\mum$, respectively