• Journal of IKEEE
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• v.15 no.4
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• pp.330-338
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• 2011

In this paper, a current-mode buck-boost converter using Multiple switching devices is presented. The efficiency of the proposed converter is higher than that of conventional buck-boost converter. In order to improve the power efficiency at the high current level, the proposed converter is controlled with PWM(pulse width modulation) method. The converter has maximum output current 300mA, input voltage 3.3V, output voltage from 700mV to 12V, 1.5MHz oscillation frequency, and maximum efficiency 90%. Moreover, this paper proposes watchdog circuits in order to ensure the reliability and to improve the performance of dc-dc converters. An electrostatic discharge(ESD) protection circuit for deep submicron CMOS technology is presented. The proposed circuit has low triggering voltage using gate-substrate biasing techniques. Simulated result shows that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS(8.2V).

• Journal of IKEEE
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• v.14 no.2
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• pp.82-89
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• 2010

In this paper, a buck-boost converter using three DTMOS(Dynamic Threshold Voltage MOSFET) switching devices is presented. The efficiency of the proposed converter is higher than that of conventional buck-boost converter. DTMOS with low on-resistance is designed to decrease conduction loss. The threshold voltage of DTMOS drops as the gate voltage increases, resulting in a much higher current handling capability than standard MOSFET. In order to improve the power efficiency at the high current level, the proposed converter is controlled with PWM(pulse width modulation) method. The converter has maximum output current 300mA, input voltage 3.3V, output voltage from 700mV to 12V, 1.2MHz oscillation frequency, and maximum efficiency 90%. Moreover, the LDO(low drop-out) is designed to increase the converting efficiency at the standby mode below 1mA.

• Journal of IKEEE
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• v.17 no.1
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• pp.77-82
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• 2013

In this paper, dc-dc buck converter controled by the peak current-mode pulse-width-modulation (PWM) presented. Based on the small-signal model, we propose the novel methods of the power stage and the systematic stability designs. To improve the reliability and performance, over-temperature and over-current protection circuits have been designed in the dc-dc converter systems. To prevent electrostatic An electrostatic discharge (ESD) protection circuit is proposed. The proposed dc-dc converter circuit exhibits low triggering voltage by using the gate-substrate biasing techniques. Throughout the circuit simulation, it confirms that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS (8.2V). The circuit simulation is performed by Mathlab and HSPICE programs utilizing the 0.35um BCD (Bipolar-CMOS-DMOS) process parameters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.129-136
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• 2005

A multiplier generator, VPM_Gen (Variable-Precision Multiplier Generator), which generates Verilog-HDL models of multiplier cores with user-defined bit-width specification, is described. The bit-widths of operands are parameterized in the range of $8-bit{\sim}32-bit$ with 1-bit step, and the product from multiplier core can be truncated in the range of $8-bit{\sim}64-bit$ with 2-bit step, resulting that the VPM_Gen can generate 3,455 multiplier cores. In the case of truncating multiplier output, by eliminating the circuits corresponding to the truncation part, the gate counts and power dissipation can be reduced by about 40% and 30%, respectively, compared with full-precision multiplier. As a result, an area-efficient and low-power multiplier core can be obtained. To minimize truncation error, an adaptive error-compensation method considering the number of truncation bits is employed. The multiplier cores generated by VPM_Gen have been verified using Xilinx FFGA board and logic analyzer.

• Journal of Sensor Science and Technology
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• v.2 no.1
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• pp.95-99
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• 1993

a-Si : H TFTs for image sensor have been fabricated and their operational characteristics have been investigated. Hydrogenated amorphous silicon nitride(a-SiN : H) films were used for the gate insulator and $n^{+}$-a-Si : H films were depostied for the source and drain contact. The thicknesses of a-SiN : H and a-Si : H films were $2000{\AA}$, respectively and the thickness of $n^{+}$-a-Si : H film was $500{\AA}$. Also the channel length and channel width of a-Si : H TFTs were $50{\mu}m$ and $1000{\mu}m$, respectively. The ON/OFF current ratio, threshold voltage, and field effect mobility of fabricated a-Si : H TFTs were $10^{5}$, 6.3 V, and $0.15cm^{2}/V{\cdot}s$, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.9
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• pp.5737-5742
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• 2015

Insert injection molding is a process in which molten plastic is injected into a mold that contains a pre-placed insert. During the injection stage, the insert can be deformed by the pressure applied by the polymer melts. The deformation of the insert changes the width of the flow path around the insert, which can cause several defects such as short shots or warpages of the parts. In order to reduce the deformation of the insert, it is important to achieve successful design of gating system, insert geometry, and molding conditions. In the present study, the insert deformations that occured during the injection molding of the BLDC motor stator were investigated by numerical analyses. The gate location and the insert shape were modified to reduce the insert deformation. Finally, the injection molding with the modified designs was carried out, and it was confirmed that the insert deformation was reduced.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.344-348
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• 2007

In this paper, we propose the electrode of the Patterned Vertical Aligned (PVA) cell [1] for high transmittance. We use the 'TechWiz LCD' for calculation of the director configuration and optical characteristics to ensure the results of the proposed electrode structure. In general, the transmittance of the PVA cell depends on the shape of the electrode and cell gap. In this work the width of gate line and data line of the improved electrode design is set to be equal to that of the PVA conventional. Instead, we modified the shape of the top and bottom electrode on order to decrease the area of the defect. For verification, we compared the calculated optical transmittance of the PVA cell with the proposed electrode structure to the conventional PVA cell . As a result, we can confirm that the optical loss due to the variation of the retardation the LC cell around electrode can be definitely decreased by the proposed electrode.

• Journal of radiological science and technology
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• v.44 no.5
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• pp.459-464
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• 2021

The detector performance is important role in acquiring the gamma rays from patients. Among parameters of detector performances, there is density, which relates to respond to gamma rays. Therefore, we confirm the detection efficiency according to various detector materials based on the density parameter using GATE (geant4 application for emission tomography) simulation tool. The NaI (density: 3.67 g/cm³), CZT (Cadimium Zinc Telluride) (density: 5.80 g/cm³), CdTe (Cadmium Telluride) (5.85 g/cm³), and GAGG (Gadoinium Aluminum Gallium Garnet) (density g/cm³) were used as detector materials. In addition, the point source and quadrant bar phantom, which is modeled for 0.5, 1.0, 1.5, and 2.0 mm thicknesses, were modeled to confirm the quatitative analysis using sensitivity (cps/MBq) and the full width at half maximum (FWHM, mm) at the 2.0 mm bar thickness containing visual evaluation. Based on the results, the sensitivity for NaI, CZT, CdTe, and GAGG detector materials were 0.12, 0.15, 0.16, and 0.18 cps/MBq. In addition, the FWHM for quadrant bar phantom in the 2.0 mm bar thickness is 3.72, 3.69, 3.70, and 3.73 mm for NaI, CZT, CdTe, and GAGG materials, respectively. Compared with performance of detector materials according to density, the high density can improve detection efficiency in terms of sensitivity and mean count. Among these detector materials, the GAGG material is efficient for detection of gamma rays.

• Journal of Korea Water Resources Association
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• v.52 no.6
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• pp.397-409
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• 2019

Gate operation of hydraulic structures is important for proper management in rivers. In this study, the characteristics of flood time were analyzed and predicted using the HEC-RAS model, which is capable of one-dimensional and two-dimensional connectivity analysis of the main points downstream of the Geum river. As a result, flood travel time was decreased once discharge increase and downstream water level rising. However, When the floodplain was overflowed, the arrival time increased due to the rapid increase of the river width. Also, the same condition, flood wave travel time at the major point was approximately twice as fast as water level rising travel time, indicating that waves progressed faster than actually water. Using the results of this study, it will be helpful in the river.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.11
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• pp.834-841
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• 2018

A power amplifier for subgigahertz short-range wireless communication using $0.18-{\mu}m$ CMOS technology is presented. It is designed as a differential structure to form easily a virtual ground node, to increase output power, and to design a cascode structure to prevent breakdown. The transistor gate width was determined to maximize the output power and power-added efficiency(PAE), and the balun was optimized through electromagnetic simulation to minimize the loss caused by the matching network. This power amplifier had a gain of more than 49.5 dB, a saturation power of 26.7 dBm, a peak PAE of 20.7 % in the frequency range of 860 to 960 MHz, and a chip size of $2.14mm^2$.