• Journal of Power Electronics
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• v.14 no.5
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• pp.937-945
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• 2014

This paper presents an optimized space vector pulse-width modulation (OSVPWM) technique for a five-level cascaded H-bridge (CHB) inverter. The space vector diagram of the five-level CHB inverter is optimized by resolving it into inner and outer two-level space vector hexagons. Unlike conventional space vector topology, the proposed technique significantly reduces the involved computational time and efforts without compromising the performance of the five-level CHB inverter. A further optimized (FOSVPWM) technique is also presented in this paper, which significantly reduces the complexity and computational efforts. The developed techniques are verified through MATLAB/SIMULINK. Results are compared with sinusoidal pulse-width modulation (SPWM) to prove the validity of the proposed technique. The proposed simulation system is realized by using an XC3S400 field-programmable gate array from Xilinx, Inc. The experiment results are then presented for verification.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.230-238
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• 2017

We have proposed an InGaAs-based gate-all-around (GAA) tunneling field-effect transistor (TFET) with a stacked dual-metal gate (DMG). The electrical performances of the proposed TFET are evaluated through technology computer-aided design (TCAD) simulations. The simulation results show that the proposed TFET demonstrates improved DC performances including high on-state current ($I_{on}$) and steep subthreshold swing (S), in comparison with a single-metal gate (SMG) TFET with higher gate metal workfunction, as it has a thinner source-channel tunneling barrier width by low workfunction of source-side channel gate. The effects of the gate workfunction on $I_{on}$, the off-state current ($I_{off}$), and S in the DMG-TFETs are examined. The DMG-TFETs with PNPN structure demonstrate outstanding DC performances and RF characteristics with a higher n-type doping concentration in the $In_{0.8}Ga_{0.2}As$ source-side channel region.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.506-508
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• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.10a
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• pp.330-335
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• 2001

Characteristics of the present world market include demanding and sophisticated customers, requirement of high quality and innovative products, greater product diversity, increasing labour and products costs, availability of diverse alternatives to the customers and smaller batch sizes to satisfy a variety of customer profiles. To fulfil these characteristics, manufacturing companies need to be flexible adaptable, proactive and able to produce variety of products in short time at low cost. The aim of the study is to develop a computer-aided design system for water-gate on AutoCAD R2000 system. The developed system has been written in AutoCAD and VisualLISP with a personal computer, and is composed four modules which are the gate-lifter input module, guide-frame input module, and upgrade module. Based on knowledge-based rules, the system is designed by considering several factors, such as width and height of a water-gate, material, object of product and maximum depth of water.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.1
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• pp.88-99
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• 2007

In this paper, a novel new pulse power generator based on IGBT stacks is proposed for pulse power application. Because it can generate up to 60kV pulse output voltage without any step- up transformer or pulse forming network, it has advantages of fast rising time, easiness of pulse width variation and rectangular pulse shape. Proposed scheme consists of series connected 9 power stages to generate maximum 60kV output pulse and one series resonant power inverter to charge DC capacitor voltage. Each power stages are configured as 8 series connected power cells and each power cell generates up to 850VDC pulse. Finally pulse output voltage is applied using total 72 series connected IGBTs. To reduce component for gate power supply, a simple and robust gate drive circuit is proposed. For gating signal synchronization, full bridge invertor and pulse transformer generates on-off signals of IGBT gating with gate power simultaneously and it has very good characteristics of short circuit protection.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.8
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• pp.57-62
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• 1993

In this paper, both feasible power gain and power added efficiency at the operating center frequency of 12 GHz are stressed to design a power FET with double-heterjunction structure. The variable parameters or the design are the unit gate width, the gate length, the doping density of AlGaAs, the AlGaAs thickness, the spacer thickness, the Al mole fraction, and the GaAs well thickness. The results of simulation for the FET with 1.mu.m gate length show that the power gain and the power added efficiency are 10.2 dB and 36.3% at 12GHz, respectively. An extrapolation of the relation between current gain and unilateral gain yields a 17 GHz cutoff frequency and 43GHz maximum frequency of oscillation. The calculation of the current versus voltage characteristics show that the output power of the device is about 0.62W.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.121-126
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• 1996

In this paper an MMIC VCO which can be used in a double conversion TV tuner is designed, fabricated and measured. The VCO is designed using the small signal method and fabricated using ETRI GaAs MMIC foundry. The 3x200$\mu$m gate width MESFET with 1$\mu$m gate length is used for an active device and MIM capacitors, spiral inductors, thin film resitors are used as passive elements. The VCO has output power of 10.95dBm at 1955 MHz with 5V bias voltage and 4V tuning voltage. The oscillation frequency change form 1947 MHz to 1964 MHz is obtaine dby an external varactor diode connected to the gate with a tuning voltage from 0 V to 6V.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2008.05a
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• pp.151-154
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• 2008

The field emission lamps have the advantages to their cold cathode-characteristic and the eco-friendly, We realized that the dual emitter system showed very simple structure which gate and cathode electrodes are formed on the same glass surface. In this paper, we reported the properties of dual emitters depended on variation of gate width and spacing for optimum panel structure. In combination of dual emitter structure and bi-polar driving, electron beam spreads more than normal gate structure or diode structure, and emission uniformity increased in dual emitter structure at 5"-diagonal.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.82-87
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• 1997

Ion-Sensitive Field-Effect Transistors(ISFETs) with LPCVD silicon nitride as a sensitive gate were fabricated on the basis of a CMOS process. The silicon nitride was deposited directly on a poly silicon gate-electrode. Using a specially designed measuring cell, the hydrogen ions sensing properties of the ISFET in liquid could be investigated without any bonding or encapsulation. At first, th sensitivity was estimated by simualtions according to the site-binding theory and the experimental results were analysed and compared with simulated results. The measured dta were in good agreement with the simulated results. The silicon nitride based ISFET has good linearity evaluated from correlation factor ($\geq$0.9998) and a mean pH-sensitivity of 56.8mV/pH. The maximum hysteresis width between forward(pH=3\longrightarrowpH=11)- and backward(pH=11\longrightarrowpH=3) titration was 16.7mV at pH=6.54.

• Journal of architectural history
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• v.21 no.4
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• pp.71-79
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• 2012

The purpose of this research is to analyse the changes of ground level of Sungnyemun, the South Gate of Seoul City, and the principles of arch scale through the investigation based on the old records in Joseon dynasty. The result of this research is as follows: 1) The ground level of Sungnyemun, refers the level of foundation stone which was confirmed as original which is verified through the excavation conducted in 2005, maintained 1m's elevated level in 15~16 century and its elevated date presumed in King Sejong's reign(1418~1450). 2) The ground level of Sungnyemun is closely related with the royal funeral ceremony. 3) The width and height scale of Sungnyemun arch is about the ratio of 1 to 1. 4) During the Joseeon dynasty, Sungnyemun was referred as standard of other city wall gate. And it has similar architectural characteristics with Heunginjimun (or East Gate) of Seoul and Hwaseong Janganmun.