• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 추계종합학술대회
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• pp.887-890
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• 2005

DGMOSFET는 CMOS 스케일링의 확장 및 단채널 효과를 보다 효과적으로 제어할 수 있는 유망란 소자이다. 특히 20nm이하의 도핑되지 않은 Si 채널에서 단채널 효과를 제어하는데 가장 효과적이다. 본 논문에서는 DGMOSFET의 해석학적 전송모델을 제시할 것이다. 단채널 효과를 해석학적으로 분석하기 위해 Subthreshold Swing(SS), 그리고 문턱전압 roll-off(${\Delta}V_{th}$) 등을 이용하였다. 여기서 제시된 모델은 이온방출효과와 source-drain 장벽을 통해 캐리어들의 양자 터널링을 포함하여 해석할 것이다. 여기서 제시된 모델은 gate길이, 채널두께, 게이트 산화막 두께 등을 설계하는데 이용할 것이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.18-26
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• 2004

Back-gated silicon-on-insulator MOSFET -a threshold-voltage adjustable device-employs a constant back-gate potential to terminate source-drain electric fields and to provide carrier confinement in the channel. This suppresses shortchannel effects of nano-scale and of high drain biases, while allowing a means to threshold voltage control. We report here a theoretical analysis of this geometry to identify its natural length scales, and correlate the theoretical results with experimental device measurements. We also analyze experimental electrical characteristics for misaligned back-gate geometries to evaluate the influence on transport behavior from the device electrostatics due to the structure and position of the back-gate. The backgate structure also operates as a floating-gate nonvolatile memory (NVRAM) when the back-gate is floating. We summarize experimental and theoretical results that show the nano-scale scaling advantages of this structure over the traditional front floating-gate NVRAM.

• 한국정보통신학회논문지
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• 제18권11호
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• pp.2709-2714
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• 2014

본 연구에서는 비대칭 이중게이트 MOSFET의 상하단 게이트 산화막 두께 비에 대한 문턱전압 및 전도중심의 변화에 대하여 분석하고자한다. 비대칭 이중게이트 MOSFET는 상하단 게이트 산화막의 두께를 다르게 제작할 수 있어 문턱전압이하 영역에서 전류를 제어할 수 있는 요소가 증가하는 장점이 있다. 상하단 게이트 산화막 두께 비에 대한 문턱전압 및 전도중심을 분석하기 위하여 포아송방정식을 이용하여 해석학적 전위분포를 구하였다. 이때 전하분포는 가우스분포함수를 이용하였다. 하단게이트 전압, 채널길이, 채널두께, 이온주입범위 및 분포편차를 파라미터로 하여 문턱전압 및 전도중심의 변화를 관찰한 결과, 문턱전압은 상하단 게이트 산화막 두께 비에 따라 큰 변화를 나타냈다. 특히 채널길이 및 채널두께의 절대값보다 비에 따라 문턱전압이 변하였으며 전도중심이 상단 게이트로 이동할 때 문턱전압은 증가하였다. 또한 분포편차보단 이온주입범위에 따라 문턱전압 및 전도중심이 크게 변화하였다.

• Journal of Advanced Marine Engineering and Technology
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• 제8권1호
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• pp.72-84
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• 1984

In this paper, the characteristics relating to the stator voltage control of a small three phase squirrel cage induction motor by means of symmetrically trggered triacs instead of antiparallel SCR's is described. A complete model of the system with 220V, $3{\phi}$, 1HP motor and triac gate control circuit has been designed and tested in the laboratory, and the experimental results are compared with the numerical values. As a result of the above investigation, it is found that the range of induction motor speed control by stator voltage control is narrow.

• 대한전자공학회논문지
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• 제11권6호
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• pp.16-24
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• 1974

본 논문은 종래의 NIC회로의 구성방법을 종합하여 일반화하는 방법으로써 파라미터 제어회로와 전압 또는 전류제어회로에 의한 NIC구성방법을 제시하였다. 그리고 FET에 의해 개방 및 단락안정형 NIC회로를 구성하고 회로해석에 의한 임피던스와 실험치를 비교하여 NIC특성을 확인하고 회로해석이 타당함을 검토 확인하였다. 또한 병렬 LC를 NIC와 직렬로 연결하여 발진상태를 실험으로 확인하고 NR에 의한 발진상태와 비교 검토하였다.

• Journal of Power Electronics
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• 제7권2호
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• pp.146-158
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• 2007

A multi-pulse GTO based voltage source converter (VSC) topology together with a fundamental frequency switching mode of gate control is a mature technology being widely used in static synchronous compensators (STATCOMs). The present practice in utility/industry is to employ a high number of pulses in the STATCOM, preferably a 48-pulse along with matching components of magnetics for dynamic reactive power compensation, voltage regulation, etc. in electrical networks. With an increase in the pulse order, need of power electronic devices and inter-facing magnetic apparatus increases multi-fold to achieve a desired operating performance. In this paper, a competitive topology with a fewer number of devices and reduced magnetics is evolved to develop an 18-pulse, 2-level $\pm$ 100MVAR STATCOM in which a GTO-VSC device is operated at fundamental frequency switching gate control. The inter-facing magnetics topology is conceptualized in two stages and with this harmonics distortion in the network is minimized to permissible IEEE-519 standard limits. This compensator is modeled, designed and simulated by a SimPowerSystems tool box in MATLAB platform and is tested for voltage regulation and power factor correction in power systems. The operating characteristics corresponding to steady state and dynamic operating conditions show an acceptable performance.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.237-244
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• 2013

A continuous, explicit drain-current equation for short-channel double-gate (DG) MOSFETs has been derived based on the explicit surface potential equation. The model is physically derived from Poisson's equation in each region of operation and adopted in the unified regional approach. The proposed model has been verified with numerical solutions, physically scalable with channel length and gate/oxide materials as well as oxide/channel thicknesses.

• 한국전기전자재료학회논문지
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• 제19권7호
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• pp.601-604
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• 2006

In this paper, we propose the single poly-Si Flash EEPROM device with a new structure which does not need the high voltage switching circuits. The device was designed, fabricated and characterized. From the measurement results, it was found that the program, the erase and the read operations worked properly. The threshold voltage was 3.1 V after the program in which the control gate and the drain were biased with 12 V and 7 V for $100{\mu}S$, respectively. And it was 0.4 V after the erase in which the control gate was grounded and the drain were biased with 11 V for $200{\mu}S$. On the other hand, it was found that the program and the erase speeds were significantly dependent on the capacitive coupling ratio between the control gate and the floating gate. The larger the capacitive coupling ratio, the higher the speeds, but the target the area per cell. The optimum structure of the cell should be chosen with the consideration of the trade-offs.

• 한국진공학회지
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• 제11권4호
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• pp.212-217
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• 2002

고신뢰성 트렌치 게이트 MOSFET을 제작하기 위해 트렌치 코너를 pull-back 공정과 수소 열처리 공정을 이용하여 트렌치 코너를 둥글게 만드는 기술을 개발하였고 이를 이용하여 균일한 트렌치 게이트 산화막을 성장시킬수 있었다. 그 결과 수소 열처리 하기 전에 항복전압이 29 V인 것이 수소 열처리한 후 약 36 V로 증가하여 항복 전압에서 약 25% 향상되었다. 그리고 트렌치 게이트를 이용한 MOSFET에서 트렌치 셀이 약 45,000개 일때 게이트와 소스에 10 V를 인가했을 때, 드레인 전류는 약 45.3 A를 얻었고, 게이트 전압의 10 V, 전류를 5 A를 인가한 상태에서 On-저항은 약 55 m$\Omega$ 얻었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.522-529
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• 2013

In this paper, simple but very effective techniques to suppress subthreshold hump effect for high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) technology are presented. Two methods are proposed to suppress subthreshold hump effect using a simple layout modification approach. First, the uniform gate oxide method is based on the concept of an H-shaped gate layout design. Second, the gate work function control method is accomplished by local ion implantation. For our experiments, $0.18{\mu}m$ 20 V class HV CMOS technology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods are very effective for elimination of the inverse narrow width effect (INWE) as well as the subthreshold hump.