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Fabrication and Characteristic Analysis of Single Poly-Si flash EEPROM

단일층 다결정 실리콘 Flash EEPROM 소자의 제작과 특성 분석

  • 권영준 (충북대학교 반도체공학과) ;
  • 정정민 (충북대학교 반도체공학과) ;
  • 박근형 (충북대학교 전기전자컴퓨터공학부)
  • Published : 2006.07.01

Abstract

In this paper, we propose the single poly-Si Flash EEPROM device with a new structure which does not need the high voltage switching circuits. The device was designed, fabricated and characterized. From the measurement results, it was found that the program, the erase and the read operations worked properly. The threshold voltage was 3.1 V after the program in which the control gate and the drain were biased with 12 V and 7 V for $100{\mu}S$, respectively. And it was 0.4 V after the erase in which the control gate was grounded and the drain were biased with 11 V for $200{\mu}S$. On the other hand, it was found that the program and the erase speeds were significantly dependent on the capacitive coupling ratio between the control gate and the floating gate. The larger the capacitive coupling ratio, the higher the speeds, but the target the area per cell. The optimum structure of the cell should be chosen with the consideration of the trade-offs.

Keywords

References

  1. P. Pavan, R. Bez, P. Olivo, and E. Zanoni, 'Flash memory cells-an overview', Proceeding of the IEEE, Vol. 85, No.8, p. 1248, 1997 https://doi.org/10.1109/5.622505
  2. S. Wolf, 'Silicon processing for the VLSI Era volume 2-Process integration', Lattice Press, p. 633, 1990
  3. W. Brown and E. Brewer, 'Nonvolatile Semiconductor Memory Technology,' Wiley-IEEE Press, p. 30, 1997
  4. B. Weinberg, 'On tunneling in metaloxide-silicon structures', J. Appl. Phys., Vol. 53, Iss. 7, p. 5052, 1982 https://doi.org/10.1063/1.331336
  5. C. Richard, 'Trimming analog circuits using floating-gate analog MOS memory', IEEE J Solid-State Circuits, Vol. 24, No.6, p. 1569, 1989 https://doi.org/10.1109/4.44992
  6. R. Jacob Baker, H. Li, and D. Boyce, 'CMOS Circuit Design, Layout and Simulation', IEEE Press, p. 469, 1998
  7. B. K. Yoshikawa. 'Comparison of current flash EEPROM erasing methods', IEDM Tech. Dig, p. 595, 1992
  8. K. Tamer San, 'Effects of erase source bias on flash EPROM device reliability', IEEE Trans., Vol. 42, No.1 p. 150, 1995
  9. 황현상, 박근형, '플레시 메모리기술', 지성출판사, 15권, 1호, p.127, 2001