• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.111-121
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• 2012

In this paper, a poly-Si thin film transistor with ${\sim}0.5{\mu}m$ gate length was fabricated and its electrical characteristics are optimized. From the results, it was verified that making active region with larger grain size using low temperature annealing is an efficient way to enhance the subthreshold swing, drain-induced barrier lowering and on-current characteristics. A SONOS flash memory was fabricated using this poly-Si channel process and its performances are analyzed. It was necessary to optimize O/N/O thickness for the reduction of electron back tunneling and the enhancement of its memory operation. The optimized device showed 2.24 V of threshold voltage memory windows which coincided with a well operating flash memory.

• Magazine of the Korean Society of Agricultural Engineers
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• v.24 no.1
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• pp.44-52
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• 1982

Recently, estuary reserovoirs have been actively constructed in Korea and also in Japan there are a large number of estuary reservoirs constructed. But most of the estuary reservoirs are located at the downstream of a river where geographical condition is best for the construction of an enclosing dam. And an effective utilization of water from the estuary reservoir seems to be difficult even if estuary reservoirs are considered to be the water resources the most available for their watershed. Studies on estuary reservoirs so far have been mainly concentrated on the physical and engineering problems of the dam construction itself. The purpose of the present study is to review the estuary reservoir planning in connection with the water resources development and to study a basis of the planning. First, the levels of water use in Korea and Japan were compared with those of other countries in the world. And then, some representative reservoirs were selected to study the roles of a reservoir and water-using conditions in the watershed. Based on the study, a survey was given on the relation between a dam construction upstream and an estuary reservoir construction downstream of a river. Finally, a comprehensive examination was made of the bases of estuary reservoir planning. (1) The estuary reservoir planning is deeply related to the plan for water use develo- pment in the watershed. After the upstream water resources were fully developed up to the most, water reso- urces development by an estuary reservoir should be started. (2) If an estuary lake has a capacity big enough, it can store flood discharge of the watershed without any loss and become a basic facility that will bring about the maxi- mum use of water from the watershed. (3) Estuary reservoirs store water used in the upstream watershed, so recycling of water use is attained by the reservoir. Water in the estuary lake is difficult to be fresh water in its long run. Therefore, estuary reservoir should be located at a place where polluted water is purified and refused. All the planning should be based on the assumption that water in the estuary lake is not fresh but polluted after a long time. (4) The estuary lake can only supply water to the lower basin directly. But the upstream area is benefited from the estuary lake by exchange of irrigation water sources between the lower and the upper area. So a large-scale exchange plan between new and existing water resources is important. By constructing estuary reservoirs and the exchange of water sources between upper and lower areas, the reasonable maximum use of water from the whole watershed is at- tained. (5) The big problem coming from the water resources development by an enclosing estuary is salt water intrusion into the lake. To maintain the estuary lake salt-free, multi-purpose use of the lake should be avoided. It is necessary to take such fundamental measures as abolition of back flow operation of gate, and the closing of the fish port and the fish ladder. The results mentioned above were found in this study and these results of this study could be used for the adequate planning of estuary reservoirs in connection with the maximum water use of the watershed.

• The Journal of the Acoustical Society of Korea
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• v.39 no.5
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• pp.414-423
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• 2020

In this paper, we propose a Dilated Convolution Gate Linear Unit (DCGLU) to mitigate the lack of sparsity and small receptive field problems caused by the segmentation map extraction process in sound event detection with weak labels. In the advent of deep learning framework, segmentation map extraction approaches have shown improved performance in noisy environments. However, these methods are forced to maintain the size of the feature map to extract the segmentation map as the model would be constructed without a pooling operation. As a result, the performance of these methods is deteriorated with a lack of sparsity and a small receptive field. To mitigate these problems, we utilize GLU to control the flow of information and Dilated Convolutional Neural Networks (DCNNs) to increase the receptive field without additional learning parameters. For the performance evaluation, we employ a URBAN-SED and self-organized bird sound dataset. The relevant experiments show that our proposed DCGLU model outperforms over other baselines. In particular, our method is shown to exhibit robustness against nature sound noises with three Signal to Noise Ratio (SNR) levels (20 dB, 10 dB and 0 dB).

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.2 s.302
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• pp.49-58
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• 2005

A new soft switching three-phase PWM rectifier with simple circuit configuration and high efficiency has been developed. The proposed circuit is a kind of the auxiliary resonant commutated Pole(ARCP)converter The conventional ARCP converter requires three-auxiliary reactors and six-auxiliary switches for the soft switching auxiliary circuit and for these switching elements, a gate drive circuit and a control circuit are required, resulting in high part as a disadvantage. In the main circuit proposed in this paper, the auxiliary soft switching circuit is composed of two-auxiliary reactors, two-auxiliary switches and several diodes. In addition, common use of the PWM control circuit for two-switches will make the control circuit of the auxiliary switches simple. By means of function of the soft switching auxiliary circuit, the main switching element performs zero voltage switching operation and the auxiliary switches perform the zero current switching. In this paper, the circuit configuration and the operational analysis of the proposed circuit are described at first and then, experimental results will be reported. By using a prototype with 5[kW] capacity, the conversion efficiency of maximum $98.8[\%]$ and the power factor of $99[\%]$ or higher were obtained.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.102-111
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.10
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• pp.719-724
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• 2016

This paper describes the performance improvement of an inrush current limiter to prevent damage or malfunctions in power converters due to the inrush current. When the power converter of military radar is operated, the circuit breaker of the power converter is often activated because the overcurrent flows through the circuit breaker of the power converter. Therefore, this study performed a cause analysis of the problem, which is a larger current flow than the intended current(250A). The operation principle of an inrush current limiter and SCR (Silicon Controlled Rectifier) used in the inrush current limiter was analyzed. As a result, the overcurrent flow through the circuit breaker was found to be due to dv/dt triggering of SCR. Based on cause analysis, this paper proposes a technique by adding the resistor in front of the SCR to prevent an unnecessary inrush current. Finally, the effectiveness of the improvement was verified by measuring the output current in the inrush current limiter. The power converter equipped with the improved inrush current limiter operated for more than 1 year without the circuit breaker of the power converter being activated.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.3
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• pp.312-320
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• 2019

In this paper, we design a 512Kb eFlash IP using 110nm eFlash cells. We proposed eFlash core circuit such as row driver circuit (CG/SL driver circuit), write BL driver circuit (write BL switch circuit and PBL switch select circuit), read BL switch circuit, and read BL S/A circuit which satisfy eFlash cell program, erase and read operation. In addition, instead of using a cross-coupled NMOS transistor as a conventional unit charge pump circuit, we propose a circuit boosting the gate of the 12V NMOS precharging transistor whose body is GND, so that the precharging node of the VPP unit charge pump is normally precharged to the voltage of VIN and thus the pumping current is increased in the VPP (boosted voltage) voltage generator circuit supplying the VPP voltage of 9.5V in the program mode and that of 11.5V in the erase mode. A 12V native NMOS pumping capacitor with a bigger pumping current and a smaller layout area than a PMOS pumping capacitor was used as the pumping capacitor. On the other hand, the layout area of the 512Kb eFlash memory IP designed based on the 110nm eFlash process is $933.22{\mu}m{\times}925{\mu}m(=0.8632mm^2)$.

• Journal of Wetlands Research
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• v.23 no.3
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• pp.213-223
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• 2021

To understand the sedimentary environment of Scirpus planiculmis habitat (Myeongji and Eulsuk tidal flats) in the Nakdong Estuary, this study analyzed the statistical parameters (sorting, skewness, and kurtosis) of grain size data and the major (Al, Fe, Mn, Mg, Ca, Na, K, Ti, and P), minor (Li, Sc, V, Cr, Co, Ni, Cu, Zn, Sr, Zr, Cs, Pb, Th, and U), and rare earth elements (REEs) in sediment cores. For Myeongji, the sediment structure of the upper part of the cores was poorly sorted, more finely skewed, and more leptokurtic due to construction of the West gate. By contrast, the Eulsuk cores all differed due to the contrasting floodgate operation patterns of the West and East gates. The linear discriminate function (LDF) results corresponded to the statistical parameters for grain size. At the Eulsuk tidal flat (sites ES05 and ES11), elemental distributions were representative of Al-, Fe- and Ca-associated profiles, in which the elements are largely controlled by the accumulation of their host minerals (such as Na- and K-aluminosilicate and ferromagnesium silicate) and heavy detrital minerals at the sites. Detrital minerals including the aluminosilicates are major factors in the elemental compositions at ES05, diluting the REE contents. However, clay minerals and Fe-oxyhydroxides, as well as REE-enriched heavy minerals, appeared to be controlling factors of the elemental composition at ES11. Therefore, the mineral fractionation process is important in determining the elemental composition during sedimentation, which reflects the depositional condition of riverine-saline water mixing at both sites.

• Journal of IKEEE
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• v.25 no.4
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• pp.625-633
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• 2021

This paper describes a scalable architecture for flexible hardware implementation of Montgomery modular multiplication. Our scalable modular multiplier architecture, which is based on a one-dimensional array of processing elements (PEs), performs word parallel operation and allows us to adjust computational performance and hardware complexity depending on the number of PEs used, N_PE. Based on the proposed architecture, we designed a scalable Montgomery modular multiplier (sMM) core supporting eight field sizes defined in SEC2. Synthesized with 180-nm CMOS cell library, our sMM core was implemented with 38,317 gate equivalents (GEs) and 139,390 GEs for N_PE=1 and N_PE=8, respectively. When operating with a 100 MHz clock, it was evaluated that 256-bit modular multiplications of 0.57 million times/sec for N_PE=1 and 3.5 million times/sec for N_PE=8 can be computed. Our sMM core has the advantage of enabling an optimized implementation by determining the number of PEs to be used in consideration of computational performance and hardware resources required in application fields, and it can be used as an IP (intellectual property) in scalable hardware design of elliptic curve cryptography (ECC).