• Journal of the Korean Society for Aviation and Aeronautics
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• v.26 no.4
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• pp.1-12
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• 2018

Baggage Handling System(BHS) is an important element of ground operation services and the importance is further emphasized as air demand increases and passengers change. If there is a problem with departure baggage handling, the aircraft's gate occupancy time will be longer than the initial plan, resulting in congestion of the anchorage leading to final passenger terminal and mooring and road congestion and arrival or It is delayed until the processing of the baggage of the connecting flight and it can cause an economic loss such as confusion in the operation of the airport. The purpose of this study is to investigate the effect of the perception of service quality of BHS users on public Institutions performance through user satisfaction, user performance, and user loyalty. Analysis results using Structural Equation Model was suggested and its implication was discussed in the conclusion.

• Journal of Sensor Science and Technology
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• v.32 no.4
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• pp.246-251
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• 2023

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.

• Journal of Korean Society of Disaster and Security
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• v.14 no.2
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• pp.61-75
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• 2021

Recently, as the occurrence frequency of sudden floods due to climate change increased and the aging of the existing spillway, it is necessary to establish a plan to utilize an auxiliary spillway to minimize the flood damage of downstream rivers. Most studies have been conducted on the review of flow characteristics according to the operation of auxiliary spillway through the hydraulic experiments and numerical modeling. However, the studies on examination of flood damage in the downstream rivers and the stability of the revetment according to the operation of the auxiliary spillway were relatively insufficient in the literature. In this study, the stability of the revetment on the downstream river according to the outflow conditions of the existing and auxiliary spillway was examined by using 3D numerical model, FLOW-3D. The velocity, water surface elevation and shear stress results of FLOW-3D were compared with the permissible velocity and shear stress of design criteria. It was assumed the sluice gate was fully opened. As a result of numerical simulations of various auxiliary spillway operations during flood season, the single operation of the auxiliary spillway showed the reduction effect of maximum velocity and the water surface elevation compared with the single operation of the existing spillway. The stability of the revetment on downstream was satisfied under the condition of outflow less than 45% of the design flood discharge. However, the potential overtopping damage was confirmed in the case of exceeding the 45% of the design flood discharge. Therefore, the simultaneous operation with the existing spillway was important to ensure the stability on design flood discharge condition. As a result of examining the allocation ratio and the total allowable outflow, the reduction effect of maximum velocity was confirmed on the condition, where the amount of outflow on auxiliary spillway was more than that on existing spillway. It is because the flow of downstream rivers was concentrated in the center due to the outflow of existing spillway. The permissible velocity and shear stress were satisfied under the condition of less than 77% of the design flood discharge with simultaneous operation. It was found that the flood damage of downstream rivers can be minimized by setting the amount allocated to the auxiliary spillway to be larger than the amount allocated to the existing spillway for the total outflow with simultaneous operation condition. However, this study only reviewed the flow characteristics around the revetment according to the outflow of spillway under the full opening of the sluice gate condition. Therefore, the various sluice opening conditions and outflow scenarios will be asked to derive more efficient utilization of the auxiliary spillway in th future.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5389-5396
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• 2012

In this paper, an optimized residual data decoder architecture is proposed to improve the performance in H.264/AVC. The proposed architecture is an integrated architecture that combined parallel inverse transform architecture and parallel inverse quantization architecture with common operation units applied new inverse quantization equations. The equations without division operation can reduce execution time and quantity of operation for inverse quantization process. The common operation unit uses multiplier and left shifter for the equations. The inverse quantization architecture with four common operation units can reduce execution cycle of inverse quantization to one cycle. The inverse transform architecture consists of eight inverse transform operation units. Therefore, the architecture can reduce the execution cycle of inverse transform to one cycle. Because inverse quantization operation and inverse transform operation are concurrency, the execution cycle of inverse transform and inverse quantization operation for one $4{\times}4$ block is one cycle. The proposed architecture is synthesized using Magnachip 0.18um CMOS technology. The gate count and the critical path delay of the architecture are 21.9k and 5.5ns, respectively. The throughput of the architecture can achieve 2.89Gpixels/sec at the maximum clock frequency of 181MHz. As the result of measuring the performance of the proposed architecture using the extracted data from JM 9.4, the execution cycle of the proposed architecture is about 88.5% less than that of the existing designs.

• ETRI Journal
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• v.25 no.3
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• pp.203-209
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• 2003

This paper reports on our investigation of DC and RF characteristics of p-channel metal oxide semiconductor field effect transistors (pMOSFETs) with a compressively strained $Si_{0.8}Ge_{0.2}$ channel. Because of enhanced hole mobility in the $Si_{0.8}Ge_{0.2}$ buried layer, the $Si_{0.8}Ge_{0.2}$ pMOSFET showed improved DC and RF characteristics. We demonstrate that the 1/f noise in the $Si_{0.8}Ge_{0.2}$ pMOSFET was much lower than that in the all-Si counterpart, regardless of gate-oxide degradation by electrical stress. These results suggest that the $Si_{0.8}Ge_{0.2}$ pMOSFET is suitable for RF applications that require high speed and low 1/f noise.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.621-627
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• 2010

This paper proposes an efficient architecture of Inter layer up-sampling in decoder for SVC(scalable video coding). A register bank for horizontal and vertical up-sampling and interpolation units are designed, by introducing the proposed architecture, 41% memory bandwidth is reduced compared to JSVM. For real-time operation for HD 6 layer decoder having CIF, SD, HD resolution for CGS layer, the hardware is designed to operate at 127MHz. The gate count is about 3000.

• Journal of Electrical Engineering and Technology
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• v.7 no.4
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• pp.538-545
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• 2012

In this paper a novel cascaded transformer multilevel inverter is proposed. Each basic unit of the inverter includes two DC sources, single phase transformers and semiconductor switches. This inverter, which operates as symmetric and asymmetric, can output more number of voltage levels in the same number of the switching devices. Besides, the number of gate driving circuits is reduced, which leads to circuit size reduction and lower power consumption in the driving circuits. Moreover, several methods to determination of transformers turn ratio in proposed inverter are presented. Theoretical analysis, simulation results using MATLAB/SIMULINK and experimental results are provided to verify the operation of the suggested inverter.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.111-114
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• 2000

Single Electron Transistor Logic (SETL) can be characterized by HSPICE simulation using a SPICE macro model. First, One unit SET is characterized by Monte-carlo simulation and then we fit SPICE macro-modeling equations to its characteristics. Second, using this unit SET, we simulate the transient characteristics of two-input NAND gate in both the static and dynamic logic schemes. The dynamic logic scheme shows more stable operation in terms of logic-swing and on/off current ratio. Also, there is a merit that we can use the SET only as current on-off switch without considering the voltage gain.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.140-145
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• 2002

A new CMOS buffer removing short-circuit power consumption is proposed. The gate-driving signal of the pull-up(pull-down) transistor at the output is controlled by delayed internal signal to get tri-state output momentarily by shunting off the path of the short-circuit current. The SPICE simulation results verified the operation of the proposed buffer and showed the enhancement of the power-delay product at 3.3V supply voltage about 42% comparing to the conventional tapered CMOS buffer(1).

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.89-90
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• 2013

Higher power density, higher operational temperature, lower on state resistance and higher switching frequency capabilities of Silicon Carbide (SiC) technology devices compared to Silicon (Si) devices makes it has higher promising market. One of the most developed SiC devices is the power MOSFET. This study tests the SiC MOSFET under short circuit conditions taking into account the effect of gate voltage characteristics. The results will be compared to IGBT and MOSFET Si devices with similar ratings. A tester circuit was designed to perform the short circuit operation.