Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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An Efficient Architecture of Inter Layer Up-sampling in Scalable Video Decoder

SVC 복호화기에서 Inter Layer 업-샘플링의 효과적인 구조

  • 기대욱 (부산대학교 전자전기공학과) ;
  • 김재호 (부산대학교 전자전기공학과)
  • Received : 2009.10.21
  • Accepted : 2010.02.10
  • Published : 2010.03.31
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Abstract

This paper proposes an efficient architecture of Inter layer up-sampling in decoder for SVC(scalable video coding). A register bank for horizontal and vertical up-sampling and interpolation units are designed, by introducing the proposed architecture, 41% memory bandwidth is reduced compared to JSVM. For real-time operation for HD 6 layer decoder having CIF, SD, HD resolution for CGS layer, the hardware is designed to operate at 127MHz. The gate count is about 3000.

본 논문에서는 SVC 복호화기에서 각 계층간 Inter layer 업-샘플링을 효과적으로 구현하기 위한 하드웨어 구조를 제안한다. 제안하는 구조에서 수직, 수평 방향 업-샘플링을 위한 register bank와 보간 모듈이 설계된다. 제안 구조를 사용하여 SRAM 메모리가 감소되고 JSVM과 비교해서 약 41%의 메모리 밴드위스가 감소되었다.

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References

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