• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.105-108
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• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.741-744
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• 1999

In this paper, We represent a low complexity of parallel canonical basis multiplier for GF( q$^{n}$ ), ( q＞ 2). The Mastrovito multiplier is investigated and applied to multiplication in GF(q$^{n}$ ), GF(q$^{n}$ ) is different with GF(2$^{n}$ ), when MVL is applied to finite field. If q is larger than 2, inverse should be considered. Optimized irreducible polynomial can reduce number of operation. In this paper we describe a method for choosing optimized irreducible polynomial and modularizing recursive polynomial operation. A optimized irreducible polynomial is provided which perform modulo reduction with low complexity. As a result, multiplier for fields GF(q$^{n}$ ) with low gate counts. and low delays are constructed. The architectures are highly modular and thus well suited for VLSI implementation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.286-291
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• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• Journal of the Korea Institute of Military Science and Technology
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• v.16 no.1
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• pp.81-88
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• 2013

This paper describes the fundamentals, design, realization and test results of a BPSK(Bi Phase Shift Keying) transceiver for the direction finding proximity fuze sensor for anti-aircrafts or air missiles. The BPSK transceiver for the direction finding fuze sensor has been designed to detect a moving target by Doppler signal processing with the code correlation method and to distinguish direction by comparing received powers of each Doppler signal from adjacent three receiving antennas. The electrical and ESS(Environmental Stress Screening) tests of the BPSK transceiver showed satisfactory results and target detection and direction finding performances proved to be successful through dynamic operation tests by 155 mm gun firing.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.9
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• pp.771-774
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 $\mu\textrm{m}$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.30 no.4
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• pp.30-38
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• 2007

In this study, we propose an RFID based container terminal operation process. Field tests are conducted for 900 MHz (truck identification) tag and 433 MHz RFID (container identification/e-seal) tag at an Incheon container terminal to verify possibility of applying RFID in the container terminal gate. To evaluate effect of applying RFID in the container terminal operation, simulation models for current and RFID based container terminals are developed using ARENA. Simulations are carried out using industrial field data and the result indicates that performance of the container terminal can be prominently improved after RFID application.

• International Journal of Fluid Machinery and Systems
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• v.3 no.4
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• pp.332-341
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• 2010

Standard dimensionless parameters cannot simultaneously represent all operation modes of a pump-turbine. They either have singularities at E=0 and multiple values in the 'unstable' areas, or else get singular at n=0. P. Suter (1966) introduced an alternative set of variables which avoids singularity and always remains unique-valued. This works for non-regulated pumps but not so well for regulated machines. A modification by C.S. Martin avoids distortion at low load. The present paper describes further improvements for the representation of torque, and for closed gate (where Suter's concept does not work). The possibility to interpolate across all operation modes is likewise useful for representing other mechanical parameters of the machine. Practical application for guide vane torque and pressure pulsation data is demonstrated by examples.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.1
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• pp.80-84
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• 2012

Recently, the small scale photovoltaic (PV) electronic devices are drawing attention as the upcoming PV generation system. The PV system is commonly used in small scale PV applications such as LED lighting and cell phone. This paper proposes photovoltaic output sensorless (POS) maximum power point tracking (MPPT) control for a small scale charging system of PV-nickel metal hydride battery using field-programmable gate array (FPGA) controller. A converter is connected to a small scale PV cell and battery, and performs the POS MPPT at the battery terminal current instead of being at the PV cell output voltage and current. The FPGA controller and converter operate based on POS MPPT method. The experimental results show that the nickel metal hydride battery is charged by the maximum PV output power.

• Journal of Korean Society on Water Environment
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• v.29 no.6
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• pp.799-807
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• 2013

Reservoir sedimentation is one of the major concerns for sustainable reservoir operation. Since sediment concentration of the rivers in the Himalayan Mountain is very high, a proper sediment management scheme is necessary. This paper presents long-term reservoir sedimentation and sediment flushing based on the gate operation. Focused on the reservoir to be constructed for the Patrind hydropower project in Pakistan, 4 different flushing scenarios were proposed in this study to prevent successive sedimentation. By extending flushing period and by increasing the flushing discharge for 2 times, the flushing rate increases up to 53.2% and 43.6% in proportion to flushing period and discharge, respectively. Based on the simulation presented in this paper, it is expected to establish efficient sediment management plan to increase hydro power generation and sediment flushing simultaneously.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.1
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• pp.9-15
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• 2021

In multi-string light-emitting diode (LED) driver system, current balancing is crucial because the brightness of LED is directly related to its forward current. This paper presents a novel LED current balancing topology using current-fed Z-source converter. With the proposed structure, currents flowing through two LED strings are automatically balanced owing to the charge-balance condition on capacitors. Operation of the proposed converter is simple and the proposed converter uses only one active switch and one diode. Moreover, low-side gate driving can be used to operate the active switch. To verify the operation of the proposed LED current balancing converter, a prototype is built and tested with different numbers of LEDs.