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Programming Characteristics of the Multi-bit Devices Based on SONOS Structure

SONOS 구조를 갖는 멀티 비트 소자의 프로그래밍 특성

  • 김주연 (울산과학대학교 전기전자통신학부)
  • Published : 2003.09.01

Abstract

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 $\mu\textrm{m}$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

Keywords

References

  1. IEEE Acrospace Conference Proceedings v.5 Retention reliability enhanced SONOS NVSM with scaled programming voltage J.Bu;M.H.White
  2. the International Conference on Solid State Devices and Materials NROM : a 2-bit trapping stroage NVM cell, give a real challenge to floating gate cells B.Eitan;P.Pavan;I.Boloom;E.Aloni;A.Frommer;D.Finzi
  3. IEEE Non-Volatile Semiconductor Memory Workshop MONOS memory cell scalable to 0.1㎛ and beyond I.Fujiwara;H.Aozasa;A.Nakamura;Y.Hayashi;T.Kobayashi
  4. IEEE Electron Device Letters High performance SONOS memory cells free of drain turn-on over-erase: compatibility issue with current flash technology M.K.Cho;D.M.Kim
  5. IEEE EDL v.22 no.11 Characterization of channel got electron injection by the subthreshold slope of NROM™ device E.Lusky;Y.Shacham Diamand;I.Bloom https://doi.org/10.1109/55.962662
  6. Lattice v.3 Silicon Processing for the VLSI Era S.Wolf
  7. IEEE International NVM Technology Conference True low-voltage flash memory operations M.H.Chi;A.Bergemnont