• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.869-875
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• 2017

Using TCAD simulation, performances of tunnel field-effect transistors (TFETs) was investigated. Drain current-gate voltage types of TFET structure such as single-gate TFET (SG-TFET), double-gate TFET (DG-TFET), L-shaped TFET (L-TFET), and Pocket-TFET (P-TFET) are simulated, and then as dielectric constant of gate oxide and channel length are varied their subthreshold swing (SS) and on-current ($I_{on}$) are compared. On-currents and subthreshold swings of the L-TFET and P-TFET structures with high electric constant and line tunneling were 10 times and 20 mV/dec more than those of the SG-TFET and DG-TFET using point tunneling, respectively. Especially, it is shown that hump effect which dominant current element changes from point tunneling to line tunneling, is disappeared in P-TFET with high-k gate oxide such as $HfO_2$. The analysis of 4 types of TFET structure provides guidelines for the design of new types of TFET structure which concentrate on line tunneling by minimizing point tunneling.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.265-275
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• 2010

In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.639-644
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• 2011

By the development of the information superhighway, the current data communication system can be exchanged data quickly and precisely between subscribers. In this paper, LVTTL(Low Voltage Transistor Transistor Logic), Using the fundamental one logic at several kinds of used in communication systems, the LVTTL transmission characteristics were measured by according to the change data transfer rate and the transmission line length. Because the transmission line length required on the current system is 30cm, We analysed LVTTL data transfer characteristics according to the transmission line length required on the current system. The amplitude level of LVTTL at 10Mbps is 3V and 50Mbps is 2.2V and 100Mbps is 2V and 125Mbps is 1.5V and 150Mbps is 1.4V. The length of transmission line 30cm was stable state up to 100Mbps data transfer rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.36-44
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• 2003

This paper proposes a Viterbi decoding scheme without trace-back operations to reduce the amount of memory storing the survivor path information, and to increase the decoding speed. The proposed decoding scheme is a modified register exchange scheme, and is verified by a simulation to give the same results as those of the conventional decoders. It is compared with the conventional decoding schemes such as the trace-back and the register exchange scheme. The memory size of the proposed scheme is reduced to 1/(5 x constraint length) of that of the register exchange scheme, and the throughput is doubled compared with that of the trace-back scheme. A decoder with a code rate of 2/3, a constraint length, K＝3 and a trace-back depth of 15 is designed using VHDL and implemented in an FPGA. It is also shown that the modified register exchange scheme can be applied to a block decoding scheme.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2093-2099
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• 2016

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.

• Ecology and Resilient Infrastructure
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• v.5 no.4
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• pp.246-256
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• 2018

In order to analyze hydraulic characteristics of discharge coefficient, hydraulic jump height, and hydraulic jump length, accompanied sediment transport, in the under-flow type vertical lift gate, the hydraulic model experiment and dimensional analysis were performed. The correlations between Froude number and hydraulic characteristics were schematized according to the presence and absence of sediment transport; the correlation of hydraulic characteristics and non-dimensional parameters was analyzed and multiple regression formulae were developed. In the hydraulic characteristics accompanied the sediment transport, by identifying the aspect different from the case that the sediment transport is absent, we verified that it is necessary to introduce variables that can express the characteristics of sediment transport. The multiple regression equations were suggested and each determination coefficient appeared high as 0.749 for discharge coefficient, 0.896 for hydraulic jump height, and 0.955 for hydraulic jump length. In order to evaluate the applicability of the developed hydraulic characteristic equations, 95% prediction interval analysis was conducted on the measured and the calculated by regression equations, and it was determined that NSE (Nash-Sutcliffe Efficiency), RMSE (root mean square), and MAPE (mean absolute percentage error) are appropriate, for the accuracy analysis related to the prediction on hydraulic characteristics of discharge coefficient, hydraulic jump height and length.

• Journal of Advanced Navigation Technology
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• v.21 no.6
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• pp.659-665
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• 2017

In this paper, a low complexity fast Fourier transform(FFT) processor is proposed for multiple input multiple output(MIMO) systems. The IEEE 802.11ac standard has been adopted along with the demand for a system capable of high channel capacity and Gbps transmission in order to utilize various multimedia services using a wireless LAN. The proposed scalable FFT processor can support the variable length of 64, 128, 256, and 512 for 8x8 antenna configuration as specified in IEEE 802.11ac standard with MIMO-OFDM scheme. By reducing the required number of non-trivial multipliers with mixed-radix(MR) and multipath delay commutator(MDC) architecture, the complexity of the proposed FFT processor was dramatically decreased. Implementation results show that the proposed FFT processor can reduced the logic gate count by 50%, compared with the radix-2 SDF FFT processor. Also, compared with the 8-channel MR-2/2/2/4/2/4/2 MDC processor and 8-channel MR-2/2/2/8/8 MDC processor, it is shown that the gate count is reduced by 18% and 17% respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.1-7
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• 2006

3-dimensional(3-D) simulations of ideal double-gate bulk FinFET were performed extensively and the electrical characteristics. were analyzed. In 3-D device simulation, we changed gate length($L_g$), height($H_g$), and channel doping concentration($N_b$) to see the behaviors of the threshold voltage($V_{th}$), DIBL(drain induced barrier lowering), and SS(subthreshold swing) with source/drain junction depth($X_{jSDE}$). When the $H_g$ is changed from 30 nm to 45nm, the variation gives a little change in $V_{th}$(less than 20 mV). The DIBL and SS were degraded rapidly as the $X_{jSDE}$ is deeper than $H_g$ at low fin body doping($1{\times}10^{16}cm^{-3}{\sim}1{\times}10^{17}cm^{-3}$). By adopting local doping at ${\sim}10nm$ under the $H_g$, the degradation could be suppressed significantly. The local doping also alleviated $V_{th}$ lowering by the shallower $X_{jSDE}\;than\;H_g$ at low fin body doping.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.537-541
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• 2003

The a-Si:H TFTs using ferroelectric of SrTiO$_3$, as a gate insulator is fabricated on glass. Dielectric characteristics of ferroelectric is better than SiO$_2$, SiN. Ferroelectric increases ON-current, decreases threshold voltage of TFT and also breakdown characteristics. The a-Si:H deposited by PECVD shows absorption band peaks at wavenumber 2,000 $cm^{-1}$ /, 635 $cm^{-1}$ / and 876 $cm^{-1}$ / according to FTIR measurement. Wavenumber 2,000 $cm^{-1}$ /, 635 $cm^{-1}$ / are caused by stretching and rocking mode SiH1. The wavenumber of weaker band, 876 $cm^{-1}$ / is due to SiH$_2$ vibration mode. The a-SiN:H has optical bandgap of 2.61 eV, refractive index of 1.8 - 2.0 and resistivity of 10$^{11}$ - 10$^{15}$ aim respectively. Insulating characteristics of ferroelectric is excellent because dielectric constant of ferroelectric is about 60 - 100 and breakdown strength is over 1 MV/cm. TFT using ferroelectric has channel length of 8 - 20 $\mu$m and channel width of 80 - 200 $\mu$m. And it shows drain current of 3 $\mu$A at 20 gate voltages, Ion/Ioff ratio of 10$^{5}$ - 10$^{6}$ and Vth of 4 - 5 volts.

• Journal of Korea Water Resources Association
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• v.31 no.4
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• pp.397-406
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• 1998

The Pyokkolche Reservoir was constructed as a major public project of the ancient agricultural society, 1600 years ago. From a hydraulic point of view, it is considered to have been carried out with a distinguished technology. It should be in particular noticed that for a consecutive banking the main stream was diverted and drained to the Yonpo stream and the dam with same sea levels on its top along the whole length was built in a nearly straight line in spite of the different sea levels between both ends on the bottom. These suggest that the carrying out artifice and surveying technigue of those days were considerably excellent. However, the insufficient plan and design at the time of the construction, the temporary management and the repeated repair works in the later ages caused the Pyokkolche to lose its function. The Changsaenggeo and Kyungjanggeo gate sites being the facilities for sluices composed of a simple span and a vertical lift hand-operated sing a pully. The advantage of the geographical characteristics at both ends of the main dam was scientifically taken to these sites which also functioned as a spillway against a flood. The gate site of Suyogeo must have been located in an entrance to Suwolri, the northern end of the Pyokkolche and Yutonggeo is presumed to have been located on the right of Sangsori, the southern end of the Pyokklche. Keywords : Pyokkolche Reservoir, construction technology, gate site location.