• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.239-239
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• 2013

For more than four decades, ion-sensitive field-effect transistor (ISFET) sensors that respond to the change of surface potential on a membrane have been intensively investigated in the chemical, environmental, and biological spheres, because of their potential, in particular their compatibility with CMOS manufacturing technology. Here, we demonstrate a new type of ISFET with dual-gate (DG) structure fabricated on ultra-thin body (UTB), which highly boosts sensitivity, as well as enhancing chemical stability. The classic ion-sensitive field-effect transistor (ISFET) has been confronted with chronic problems; the Nernstian response, and detection limit with in the Debye length. The super-coupling effects imposed on the ultra thin film serve to not only maximize sensitivity of the DG ISFET, but also to strongly suppress its leakage currents, leading to a better chemical stability. This geometry will allow the ISFET based biosensor platform to continue enhancement into the next decade.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.745-748
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• 2014

본 연구에서는 비대칭 이중게이트(double gate; DG) MOSFET의 채널길이에 대한 문턱전압이하 스윙의 변화에 대하여 분석하였다. 문턱전압이하 스윙은 트랜지스터의 디지털특성을 결정하는 중요한 요소로서 채널길이가 감소하면 특성이 저하되는 문제가 나타나고 있다. 이러한 문제를 해결하기 위하여 개발된 DGMOSFET의 문턱전압이하 스윙의 채널길이에 대한 변화를 채널두께, 산화막두께, 상하단 게이트 전압 및 도핑농도 등에 따라 조사하고자 한다. 특히 하단 게이트 구조를 상단과 달리 제작할 수 있는 비대칭 DGMOSFET에 대하여 문턱전압이하 스윙을 분석함으로써 하단 게이트 전압 및 하단 산화막 두께 등에 대하여 자세히 관찰하였다. 문턱전압이하 스윙의 해석학적 모델을 구하기 위하여 포아송방정식에서 해석학적 전위분포모델을 유도하였으며 도핑분포함수는 가우스분포함수를 사용하였다. 결과적으로 문턱전압이하 스윙은 상하단 게이트 전압 및 채널도핑농도 그리고 채널의 크기에 매우 민감하게 변화하고 있다는 것을 알 수 있었다.

• Journal of IKEEE
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• v.19 no.2
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• pp.265-270
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• 2015

In this paper, we proposed a dual-directional SCR (silicon-controlled rectifier) based ESD (electrostatic discharge) protection circuit. In comparison with conventional SCR, this ESD protection circuit can provide an effective protection against ESD pulses in the two opposite directions, so the ESD protection circuit can be discharged in two opposite direction. The proposed circuit has a higher holding voltage characteristic than conventional SCR. These characteristic enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. it was analyzed to figure out electrical characteristics in term of individual design parameters. They are investigated by using the Synopsys TCAD simulator. In the simulation results, it has trigger voltage of 6.5V and holding voltage increased with different design parameters. The holding voltage of the proposed circuit changes from 2.1V to 6.3V and the proposed circuit has symmetrical I-V characteristic for positive and negative ESD pulse.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.86-90
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• 2011

The effects of cations are very important in field-effect transistors (FETs) type DNA sensors detecting the intrinsic negative charge between single-stranded DNA and double-stranded DNA without labeling, because the intrinsic negative charge of DNA is neutralized by cations in electrolyte solution. We consider the Debye length, which depends on the concentration of cations in solution, to detect DNA hybridization based on the intrinsic negative charge of DNA. The Debye length is longer in buffer solution with a lower concentration of NaCl and the intrinsic negative charge of DNA is more effective on the channel surface in longer Debye length solution. The shifts in the gate voltage by DNA hybridization with complementary target DNA are 21 mV in 1 mM NaCl buffer solution, 7.2 mV in 10 mM NaCl buffer solution, and 5.1 mV in 100 mM NaCl buffer solution. The sensitivity of FETs to detect DNA hybridization based on charge detection without labeling depends on the Debye length.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.693-695
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• 2012

This paper have presented the breakdown voltage for double gate(DG) MOSFET. The analytical solution of Poisson's equation and Fulop's breakdown condition have been used to analyze for breakdown voltage. The double gate(DG) MOSFET as the device to be able to use until nano scale has the adventage to reduce the short channel effects. But we need the study for the breakdown voltage of DGMOSFET since the decrease of the breakdown voltage is unavoidable. To approximate with experimental values, we have used the Gaussian function as charge distribution for Poisson's equation, and the change of breakdown voltage has been observed for device geometry. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. As a result to observe the breakdown voltage, the smaller channel length and the higher doping concentration become, the smaller the breakdown voltage becomes. Also we have observed the change od the breakdown voltage for gate oxide thickness and channel thickness.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.156-164
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• 2014

In a delay line type of a time-to-digital converter implemented in Field Programmable Gate Array, the timing accuracy decreases for a longer carry chain. In this paper, we propose a structure that has a multi-phase clock and a state machine to check metastability; this would reduce the required length of the carry chain with the same time resolution. To reduce the errors caused by the time difference in the four delay lines associated with a four-phase clock, the proposed TDC generates a single input pulse from four phase clocks and uses a single delay line. Moreover, the state machine is designed to find the phase clock that is used to generate the single input pulse and determine the metastable state without a synchronizer. With the measurement range of 1 ms, the measured resolution was 22 ps, and the non-linearity was 25 ps.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.2015-2020
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• 2012

The subthreshold characteristics has been analyzed to investigate the effect of two gate in Double Gate MOSFET using impact factor based on scaling theory. The charge distribution of Gaussian function validated in previous researches has been used to obtain potential distribution in Poisson equation. The potential distribution was used to investigate the short channel effects such as threshold voltage roll-off, subthreshold swings and drain induced barrier lowering by varying impact factor for scaling factor. The impact factor of 0.1~1.0 for channel length and 1.0~2.0 for channel thickness are used to fit structural feature of DGMOSFET. The simulation result showed that the subthreshold swings are mostly effected by impact factor but are nearly constant for scaling factors. And threshold voltage roll-off and drain induced barrier lowering are also effected by both impact factor and scaling factor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.869-872
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• 2006

In this paper, the threshold voltage roll-off been analyzed for nano structure double gate FinFET. The analytical current model has been developed , including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics are used to calculate thermionic emission current, and WKB(Wentzel- framers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off Is very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects and this process has to be developed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.760-765
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• 2007

In this paper, the threshold voltage roll-off and drain induced barrier lowering(DIBL) have been analyzed for nano structure double gate FinFET. The analytical current model has been developed, including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics were used to calculate thermionic omission current, and WKB(Wentzel- Kramers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off and DIBL are very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects, and this process has to be developed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1599-1604
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• 2008

In this paper, it has been analyzed how transport characteristics is influenced on gate oxide properties in the subthreshold region as nano structure FinFET is fabricated. The analytical model is used to derive transport model, and Possion equation is used to obtain analytical model. The thermionic emission and tunneling current to have an influence on subthreshold current conduction are analyzed for nano-structure FinFET, and subthreshold swings of this paper are compared with those of two dimensional simulation to verify this model. As a result, transport model presented in this paper is good agreement with two dimensional simulation model, and this study shows that the transport characteristics have been changed by gate oxide properties. As gate length becomes smaller, funneling characteristics, one of the most important transport mechanism, have been analyzed.