• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1996년도 추계학술대회 논문집 학회본부
• /
• pp.235-238
• /
• 1996

An inverted double channel AIGaAs/lnGaAs/GaAs heterostructure grown by LP-MOCVD is demonstrated and discussed. Sheet carrier densities in excess of $4.5{\times}10^{12}cm^{-2}$ at 300K are obtained with a hall mobility of $5010cm^2/V{\cdot}s$. The proposed device with a $1.8{\times}200{\mu}m^2$ gate dimension reveals an extrinsic transconductance as high as 320 mS/mm and a saturation current density as high as 820 mA/mm at 300K. This is the highest current density ever reported for GaAs MODFET's with the same gate length. Significantly improvements on gate voltage swing (up to 3.5 V) and on reverse breakdown voltage (-10V) are demonstrated due to inverted structure.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
• /
• pp.240.1-240.1
• /
• 2013

본 연구에서는 Symmetric NMOSFET의 channel length에 따른 전기적 특성 분석에 관한 연구를 진행하였다. 특성 분석에 사용된 소자의 Gate oxide 두께는 6 nm 이며, 채널 Width/Length는 각각 10/10 ${\mu}m$, 10/0.2 ${\mu}m$ 이다. Drain Avalanche Hot Carrier(DAHC) 테스트를 진행하기 위하여 각각 스트레스 조건을 추출하였고, 조건에 해당되는 스트레스를 1700초 동안 인가하였다. 스트레스 후, Channel length가 10 ${\mu}m$과 0.2 ${\mu}m$인 두 소자의 특성을 측정, 분석결과 10 ${\mu}m$의 소자의 경우 문턱전압(VT)과 Subthreshold swing (SS)의 변화가 없었지만 0.2 ${\mu}m$의 소자의 경우 0.42V의 (from 0.67V to 1.09V) 문턱전압 변화 (VTH)와 71 mV/dec (from 79 mV/dec to 150 mV/dec))의 Swing (SS)변화를 보여 스트레스 후에 Interface trap이 증가하였음을 알 수 있다. off-state leakage current를 측정 결과 0.2 ${\mu}m$ 의 경우 leakage current의 양이 증가하였음을 알 수 있고 이는 드레인 부근에 증가된 interface trap에 의한 현상으로 판단된다. 상기 결과와 같이 DAHC 스트레스에 의한 소자의 열화 현상은 Channel length가 짧을수록 더 크게 의존하는 것을 확인하였다.

• ETRI Journal
• /
• 제38권4호
• /
• pp.675-684
• /
• 2016

This paper demonstrates the effect of fluoride-based plasma treatment on the performance of $Al_2O_3/AlGaN/GaN$ metal-insulator-semiconductor heterostructure field effect transistors (MISHFETs) with a T-shaped gate length of $0.20{\mu}m$. For the fabrication of the MISHFET, an $Al_2O_3$ layer as a gate dielectric was deposited using atomic layer deposition, which greatly decreases the gate leakage current, followed by the deposition of the silicon nitride layer. The silicon nitride layer on the gate foot region was then selectively removed through a reactive ion etching technique using $CF_4$ plasma. The etching process was continued for a longer period of time even after the complete removal of the silicon nitride layer to expose the $Al_2O_3$ gate dielectric layer to the plasma environment. The thickness of the $Al_2O_3$ gate dielectric layer was slowly reduced during the plasma exposure. Through this plasma treatment, the device exhibited a threshold voltage shift of 3.1 V in the positive direction, an increase of 50 mS/mm in trans conductance, a degraded off-state performance and a larger gate leakage current compared with that of the reference device without a plasma treatment.

• 한국유체기계학회 논문집
• /
• 제15권4호
• /
• pp.12-18
• /
• 2012

This study was performed to found out the deviations for clamp-on type ultrasonic flowmeter installed in downstream of valves. It was selected three types of two-path flowmeter mainly used for K-water as test. Experiment carried out to confirmed characteristics of deviation depending on the sensor location, straight pipe length and maker for 1-path, 2-path and 4-path combined 2-path flowmeter. It was selected two kinds of valves with 100 % and 50 % opening, butterfly valves and gate valves, for flow disturbance factor. Finally, we suggested number of sensors by maker, straight pipe length and installed location of sensors satisfying the tolerance depending on the experiment results.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2009년도 추계학술대회 논문집
• /
• pp.40-40
• /
• 2009

The electrical characteristic of the conventional self-aligned polycrystalline silicon (poly-Si) TFTs are known to present several undesired effects such as large leakage current, kink effect and hot-carrier effects. In this paper, LTPS TFTs with different GOLDD length were fabricated and investigated the effect of the GOLDD. GOLDD length of 1, 1.5 and $2{\mu}m$ were used, while the thickness of the gate dielectrics($SiN_x/SiO_2$) was fixed at 65nm(40nm/25nm). The electrical characteristics show that the kink effect is reduced at the LTPS TFTs, and degradation from the hot-carrier effect was also decreased by increasing GOLDD length.

• 전자공학회논문지A
• /
• 제31A권12호
• /
• pp.106-114
• /
• 1994

The local oxidation of silicon (LOCOS) technology, which uses a silicon nitride film as an oxidation mask and a pad oxide beween the silicon nitride and the silicon substrate, has been widely used in integrated circuits for process simplicity. But, due to long brid's beak length, there are difficulties in scabilities. Many advanced isolation techniques have been wuggested for the feduction of bird's beak length. In this paper, we presented reduced bird's beak length using the polybuffered oxide and the silicon nitride as the sidewall. Also, investigating the electrical behavior of the parasitic Al-gate MOSFET on LOCOS, we proved the validity for new isolation process.

• 전자공학회논문지A
• /
• 제32A권8호
• /
• pp.126-132
• /
• 1995

The electrical stress of short channel polycrystalline silicon (poly-Si) thin film transistor (TFT) has been investigated. The device characteristics of short channel poly-Si TFT with 5$\mu$m channel length has been observed to be significantly degraded such as a large shift in threshold voltage and asymmetric phenomena after the electrical stress. The dominant degradation mechanism in long channel poly-Si TFT's with 10$\mu$m and 20$\mu$m channel length respectively is charage trappling in gate oxide while that in short channel device with 5.mu.m channel length is defect creation in active poly-Si layer. We propose that the increased defect density within depletion region near drain junction due to high electric field which could be evidenced by kink effect, constitutes the important reason for this significant degradation in short channel poly-Si TFT. The proposed model is verified by comparing the amounts of the defect creation and the charge trapping from the strechout voltage.

• Journal of information and communication convergence engineering
• /
• 제9권6호
• /
• pp.733-737
• /
• 2011

This paper has studied subthreshold characteristics for double gate(DG) MOSFET using Gaussian function in solving Poisson's equation. Typical two dimensional analytical transport models have been presented for symmetrical Double Gate MOSFETs (DGMOSFETs). Subthreshold swing and threshold voltage are very important factors for digital devices because of determination of ON and OFF. In general, subthreshold swings have to be under 100mV/dec, and threshold voltage roll-off small in short channel devices. These models are used to obtain the change of subthreshold swings and threshold voltage for DGMOSFET according to channel doping profiles. Also subthreshold swings and threshold voltages have been analyzed for device parameters such as channel length, channel thickness and channel doping profiles.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
• /
• pp.129-132
• /
• 2000

In this paper, a 1.8㎓ low noise amplifier was designed and simulated using 0.2$\mu\textrm{m}$ Si CMOS process. Noise characteristics and s parameters were extracted for the 300$\mu\textrm{m}$ gate width and 0.25$\mu\textrm{m}$ gate length NMOS transistors. For high available power gain, each stage was designed cascode type. It revealed available power gain of 23.5dB, noise figure of 2.0dB, power consumption of 15㎽ at 2.5V. It was shown that designed low noise amplifier had good RF performance. Designed Si CMOS LNA is expected to be used for RF front-end in transceiver.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
• /
• pp.88-91
• /
• 2000

An MMIC oscillator operating at the 24.55 GHz has been designed using 0.2 ${\mu}{\textrm}{m}$AlGaAs/InGaAs/GaAs Pseudomorphic HEMT technology. The active device used in the oscillator design has a 0.2 ${\mu}{\textrm}{m}$ gate length PHEMT with 4$\times$80 ${\mu}{\textrm}{m}$ gate width. We obtained 4.08 dB of S$_{21}$ gain and 317 mS/mm of transconductance, and extrapolated unit current gain cut-off frequency (f$_{T}$) and maximum oscillation frequency (fmax) were 62 GHz and 120 GHz, respectively. The circuit are based on a series feedback and negative resistance topology. Microstrip line open stub is used to terminating. The oscillator circuits has designed for delivering maximum power to load and conjugated matching. The simulated small signal negative resistance was 50 Ω. We obtained 1.002 of loop gain and 0.0005$^{\circ}$angle from the simulation by HP libra 6.1. The layout for oscillator is 1.2$\times$1.8 $\textrm{mm}^2$.>.