• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.817-820
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• 2005

The gate-length dependence of maximun oscillation frequency $f_{MAX}$ is modeled by using scaling equations of equivalent-circuit parameters extracted from measured S-parameters of Nano-scale MOSFETs. The accuracy of the modeled $f_{MAX}$ is verified by observing good agreements with measured ones. It is observed that the $f_{MAX}$ initially increases with decreasing $L_g$ and then $f_{MAX}$ becomes saturated from $L_g$ less than 65nm.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.473-481
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• 2012

For a mesa-isolated small geometry SOI MOSFET, the potentials in the silicon film, front, back, and side-wall oxide layers can be derived three-dimensionally. Using Taylor's series expansions of the trigonometric functions, the derived potentials are written in terms of the natural length that can be determined by using the derived formula. From the derived 3-D potentials, the minimum values of the front and the back surface potentials are derived and used to obtain the closed-form expressions for the front and back gate threshold voltages as functions of various device parameters and applied bias voltages. Obtained results can be found to explain the drain-induced threshold voltage roll-off and the narrow width effect of a fully depleted small geometry SOI MOSFET in a unified manner.

• Journal of information and communication convergence engineering
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• 제9권3호
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• pp.310-314
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• 2011

This paper has presented doping profile dependent threshold voltage for DGMOSFET using analytical transport model based on Gaussian function. Two dimensional analytical transport model has been derived from Poisson's equation for symmetrical Double Gate MOSFETs(DGMOSFETs). Threshold voltage roll-off is very important short channel effects(SCEs) for nano structures since it determines turn on/off of MOSFETs. Threshold voltage has to be constant with decrease of channel length, but it shows roll-off due to SCEs. This analytical transport model is used to obtain the dependence of threshold voltage on channel doping profile for DGMOSFET profiles. Also we have analyzed threshold voltage for structure of channel such as channel length and gate oxide thickness.

• 전자공학회논문지
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• 제49권12호
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• pp.173-178
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• 2012

RF 직접 추출 방법을 통해 얻은 정확한 MOSFET 기판 파라미터를 이용하여 기판저항만을 가진 BSIM4 모델은 스케일링 부정확성 때문에 넓은 영역의 게이트 길이에 적용하기에는 물리적으로 맞지 않다는 것이 증명됐다. BSIM4의 비물리적인 문제점을 제거하기 위해서 추가적인 유전체 기판 캐패시터를 가진 수정된 BSIM4 모델이 사용되었고, 이 모델의 물리적 타당성은 우수한 게이트 길이 scalability를 관찰함으로써 증명되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권3호
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• pp.182-188
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• 2006

An artificial neural network model for the microwave characteristics of an InGaAs/InP hemt for 70 nm gate length has been developed. The small-signal microwave parameters have been evaluated to determine the transconductance and drain-conductance. We have further investigated the frequency characteristics of the device. The neural network training have been done using the three layer architecture using Levenberg-Marqaurdt Backpropagation algorithm. The results have been compared with the experimental data, which shows a close agreement and the validity of our proposed model.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권3호
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• pp.206-209
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• 2006

This paper presents an analytical noise model for the drain thermal noise, the induced gate noise, and their correlation coefficient in deep-submicron MOSFETs, which is valid in both linear region and saturation region. The impedance field method was used to calculate the external drain thermal noise current. The effect of channel length modulation was included in the analytical equation. The noise behavior of MOSFETs with decreasing channel length was successfully predicted from our model.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.215-220
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• 2007

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.164-167
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• 1994

In this Study, we design the process of 0.1$\mu\textrm{m}$ gate length CMOS that is immunized against Latch-up, and investigate the characteristic of Latch-up of this device by the design rule of layout. Using TSUPREM4 and MEDICI, we design the device and simulate the variable characteristics of it we could understand that the characteristic of Latch-up is changed for the better by varying the critical factor of it. We also investigate the structure of CMOS that can be immunized against Latch-up.

• 한국전기전자재료학회논문지
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• 제11권1호
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• pp.26-32
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• 1998

We have studied how the characteristics degradation between effective mobility and field effect mobility of gate channel in p-MOSFET's affects the gate channel length being follow by increased stress time and increased drain-source voltage stress. The experimental results between effective and field-effect mobility were analyzed that the measurement data are identical at the point of minimum slope in threshold voltage, the other part is different, that is, the effective mobility it the faster than the field-effect mobility. Also, It was found that the effective and field-effect mobility. Also, It was found that the effective and field-effect mobility of p-MOSFET's with short channel are increased by decreased channel length, increased stress time and increased drain-source voltage stress.

• 전자공학회논문지A
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• 제33A권7호
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• pp.176-184
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• 1996

To overcome the drawbacks of conventional LDMOSFETs, we propose RESURF EDMOSFETs which can be adapted in varous circuit applications, be driven without charge pumping circuity and thowe threshold voltage can be adjusted. The devices have the diffused drift region formed by a high tmperature process before the gate oxidaton. After the polysilicon gate electrode formation, a fraction of the drift region around the gate edge is opened for supplemental self-aligned ion implantation to obtain self-aligned drift region. This leads to a shorter gate length and desirable drift region junction contour under the gate edge for minimum specific-on-resistance. In additon, a and maximize the breakdown voltage. Also, by biasing the metal field plate, we can reduce the specific-on-resistance further. The devices are optimized by using the TSUPREM-4 process simulator and the MEDICI device simulator. The optimized devices have the breakdwon voltage and the specific-on-resistance of 101.5V and 1.14m${\Omega}{\cdot}cm^{2}$, respectively for n-channel RESURF EDMOSFET, and 98V and 2.75m.ohm..cm$^{2}$ respectively for p-channel RESURF EDMOSFET. To check the validity of the simulations, we fabricated n-channel EDMOSFETs and confirmed the measured breakdown voltage of 97V and the specific-on-resistance of 1.28m${\Omega}{\cdot}cm^{2}$. These results are superior to those of any other reported power devices for smart power IC applications.