• IE interfaces
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• v.13 no.4
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• pp.608-618
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• 2000

This paper proposes a design procedure to develop the object-oriented simulator of port container terminal. The design methodology uses an object-oriented approach to support an object-oriented simulation and the design procedure consists of object scheme and event scheme. The object-scheme is a procedure to determine the structure of material flow objects and information flow objects and a relation diagram between objects that have attributes and methods. The event scheme is a procedure to define methods and to connect messages of objects. We assume that the container terminal system consists of gate, container yard, and berth and the equipment used in the container terminal are container cranes, transfer cranes, yard tractors, and trailers.

• Journal of the Korea Institute of Military Science and Technology
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• v.26 no.4
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• pp.324-334
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• 2023

In this paper, the target simulator for RF signals was developed by using VST(Vector Signal Transceiver) and set by real-time signal processing SW programs. A function to process RF signals using FPGA(Field Programmable Gate Array) board was designed. The system functions capable of data processing, raw signals monitoring, target signals(simulated range, velocity) generating and RF environments data analyzing were implemented. And the characteristics of modulated signal were analyzed in RF environment. All function of programs for processing RF signal have options to store signal data and to manage the data. The validity of the signal simulation was confirmed through verification of simulated signal results.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.329-334
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• 2016

In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator $ATLAS^{TM}$ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.751-754
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• 2003

Metamorphic HEMTs (MHEMTs) have emerged as excellent challenges for the design and fabrication of high-speed HEMTs for millimeter-wave applications. Some of improvements result from improved mobility and larger conduction band discontinuity in the channel, leading to more efficient modulation doping, better confinement, and better device performance compared with pseudomorphic HEMTs. We have studied the calibration on the DC and RF characteristics of the MHEMT device using I $n_{0.53}$G $a_{0.47}$As/I $n_{0.52}$A1$_{0.48}$As modulation-doped heterostructure on the GaAs wafer. For the optimized device performance simulation, we calibrated the device performance of 0.1-${\mu}{\textrm}{m}$ $\Gamma$-gate MHEMT fabricated in our research center using the 2D ISE-DESSIS device simulator. With this calibrated parameter set, we have obtained very good reproducibility. The device simulation on the DC and RF characteristics exhibits good reproducibility for our 0.1-${\mu}{\textrm}{m}$ -gate MHEMT device compared with the measurements. We expect that our calibration result can help design over-100-GHz MHEMT devices for better device performance.ormance.

• Journal of the Korean Vacuum Society
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• v.12 no.3
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• pp.182-192
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• 2003

A new Monte Carlo (MC) simulator for electron beam lithography process in the multi-layer resists and compound semiconductor substrates has been developed in order to fabricate and develop the high-speed PHEMT devices for millimeter-wave frequencies. For the accurate and efficient calculation of the transferred and deposited energy distribution to the multi-component and multi-layer targets by electron beams, we newly modeled for the multi-layer resists and heterogeneous multi-layer substrates. By this model, the T-shaped gate fabrication process by electron beam lithography in the PHEMT device has been simulated and analyzed. The simulation results are shown along with the SEM observations in the T-gate formation process, which verifies the new model in this paper.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.367-380
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• 2013

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

• ETRI Journal
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• v.9 no.1
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• pp.37-42
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• 1987

개인용 전자자동설계 시스팀인 EDAS_P의 schematic으로부터 직접 디지틀 회로의 논리동작을 시뮬레이션할 수 있는 게이트 레벨 논리 시뮬레이터(GLSIM_P)를 IBM PC에서 C언어를 이용하여 개발하였다. 다룰수 있는 소자로는 input clock, 일반 게이트 및 clocked 게이트, ROM, RAM, PLA등이다. 논리신호 레벨은 1, 0,*(intermediate)이다. 효율적인 논리해석을 위해 selective trace 및 event driven 방식을 도입하였으며 게이트 500개 정도까지 해석이 가능하다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.7
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• pp.32-37
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• 1993

A novel insulated gate bipolar transister (IGBT), called insulated trench cathode IGBT (ISTC-IGBT), is proposed. ISTC-IGBT has a trenched well with the shallow P$^{+}$ juction in the conventional IGBT structure. The proposed structure has the capability of effectively suppressing the parasitic thyristor latchup. The holding current of ISTC-IGBT is about 2.2 times greater than that of the conventional IGBT. Detailed analysis of the latchup characteristics of ISTC-IGBT is performed by using the two-dimensional device simulator, PISCES-II B.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1618-1620
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• 1997

A GaAs schottky diode with taper field plate is proposed to increase breakdown voltage. Breakdown voltage is calculated by device simulator MEDICI. The GaAs schottky diode with taper gate which has $5.7^{\circ}$ taper angle have shown 45% increase in the breakdown voltage compared with conventional field plate GaAs schottky diode.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.88-97
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• 1993

Electrostatic Discharge(ESD) is one of the major reliability, issues for today's VLSI production. Since the gate oxide with a thickness of 100~300$\AA$ is vulnerable to several thousand volt of ESD surge, it is necessary to control the ESD events and design an efficient protection circuit. In this paper, physical mechanism of the catastrophic ESD damage is investigated by transient analysis based upon Human Body Model(HBM). Using two-dimensional electrothermal simulator, we study the failure mechanism of the output protection devices by ESD and discuss the design issues for the optimun protection network.