• Journal of Communications and Networks
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• v.13 no.5
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• pp.481-493
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• 2011

Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.1
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• pp.81-90
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• 2002

This paper presents an Implementation of digital high-performance position sensorless control system of Reluctance Synchronous Motor(RSM) drives with Direct Torque Control(DTC). The system consists of stator flux observer, speed and torque estimator, two digital hysteresis controllers, an optimal switching look-up table, Insulated Gate Bipolar Transistor(IGBT) voltage source inverter, and TMS320C31 DSP board. The stator flux observer Is based on the combined voltage and current model with stator flux feedback adaptive control of which inputs are current and voltage sensed on motor terminal for wide speed range. In order to prove the suggested sensorless control algorithm for industrial field application, we have some simulation and actual experiment at low and high speed range. The developed high-performance speed control by fully digital system are shown a good response characteristic of control results and high performance features using 1.0[kW] RSM having 2.57 reluctance ratio of $L_d/L_q$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.372-376
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• 2018

The effects of off-state bias stress on the characteristics of p-type poly-Si TFT were investigated. To reduce the gate-induced drain leakage (GIDL) current, the off-state bias stress was changed by varying Vgs and Vds. After application of the off-state bias stress, the Vgs causing GIDL current was dramatically increased from 1 to 10 V, and thus, the Vgs margin to turn off the TFT was improved. The on-current and subthreshold swing in the aged TFT was maintained. We performed a technology computer-aided design (TCAD) simulation to describe the aged characteristics. The aged-transfer characteristics were well described by the local charge trapping. The activation energy of the GIDL current was measured for the pristine and aged characteristics. The reduced GIDL current was mainly a thermionic field-emission current.

• Journal of Electrical Engineering and Technology
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• v.9 no.5
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• pp.1471-1481
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• 2014

This paper presents the new power dissipation model of individual switching device in a high-level modular multilevel converter (MMC), which can be mostly used in voltage sourced converter (VSC) based high-voltage direct current (HVDC) system and flexible AC transmission system (FACTS). Also, the voltage balancing method based on sorting algorithm is newly proposed to advance the MMC functionalities by effectively adjusting switching variations of the sub-module (SM). The proposed power dissipation model does not fully calculate the average power dissipation for numerous switching devices in an arm module. Instead, it estimates the power dissipation of every switching element based on the inherent operational principle of SM in MMC. In other words, the power dissipation is computed in every single switching event by using the polynomial curve fitting model with minimum computational efforts and high accuracy, which are required to manage the large number of SMs. After estimating the value of power dissipation, the thermal condition of every switching element is considered in the case of external disturbance. Then, the arm modeling for high-level MMC and its control scheme is implemented with the electromagnetic transient simulation program. Finally, the case study for applying to the MMC based HVDC system is carried out to select the appropriate insulated-gate bipolar transistor (IGBT) module in a steady-state, as well as to estimate the proper thermal condition of every switching element in a transient state.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2509-2515
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• 2014

In this paper, the conventional vertical structure for VLSI circuits CMOS intend to improve the stress effects of active region and built-in threshold voltage. For these improvement, the proposed structure is shallow trench isolation of moat shape. We want to analysis the electron concentration distribution, gate bias vs energy band, thermal stress and dielectric enhanced field of thermal damage between vertical structure and proposed moat shape. Physically based models are the ambient and stress bias conditions of TCAD tool. As an analysis results, shallow trench structure were intended to be electric functions of passive as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage, are decreased the stress effects of active region. The fabricated device of based on analysis results data were the almost same characteristics of simulation results data.

• Journal of Advanced Navigation Technology
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• v.17 no.5
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• pp.560-567
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• 2013

In this paper, it is proposed the fault detection method of the ASIC, without the Test Requirement Document(TRD), extracting internal logic circuit and analyzed the function of the ASIC using the multipurpose development program and simulation. If there don't have the TRD, it is impossible to analyze the operation of the circuit and find out the fault detection in any chip. Therefore, we make the TRD based on the analyzed logic data of the ASIC, and diagnose of the ASIC circuit at the gate level through the signal control of I/O pins using the Dynamic Pattern signal. According to the experimental results of the proposed method, we is confirmed the good performance of the fault detection capabilities which applied to the non-memory circuit.

• Proceedings of the Korea Water Resources Association Conference
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• 2015.05a
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• pp.150-150
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• 2015

최근 하천의 수위조절 기능을 수행하는 보 건설이 증대되고 있다. 보는 원활한 용수공급을 위해 필수적인 구조물이지만, 하천 횡단 구조물의 특성상 유사퇴적에 의한 통수단면적 감소, 홍수위험도 증가, 수질악화 등의 문제를 내포하고 있다. 이를 해결하기 위해 유사시 유사배출이 가능하고 수문개도를 통한 통수단면적 조절로 홍수위험도를 감소시킬 수 있는 가동보를 고정보와 병용해서 적용하는 추세이다. 가동보는 수문 운영 방식에 따라 하류의 흐름상태가 다양하게 나타나며, 흐름 상태에 따라 하도 및 구조물에 미치는 영향도 달라진다. 그러나 기존 가동보 및 보 하류 구조물의 설계 시 일반적으로 수문 운영조건을 고려하지 않고, 홍수위 조건을 최악조건으로 고려하는 한계가 있다. 본 연구에서는 3차원 수치모델(FLOW-3D)을 활용하여 가동보의 운영에 따라 발생하는 다양한 흐름조건이 보 하류에 미치는 영향을 검토하고자 한다. 수치모델의 검증을 위해 기존 수행된 수리실험과의 비교를 수행하였고, 홍수위 조건(수문 전문개도) 및 관리수위 조건(수문 일부개도)에서 수치모의를 수행하였다. 보 상류, 직하류, 도수종점에서 발생하는 단면최대유속, 바닥전단 응력, Froude 수 등의 수리특성을 분석하였고, 상하류간 수심차와 수문개도높이의 비와 접근유속과 보 직하류에서 유출되는 유속의 비로 무차원화하여 관계를 분석하였다. 또한 홍수위 조건과 관리수위 조건에서 발생하는 수리특성을 비교함으로써, 보 하류부 구조물 설계 시 반영할 최악조건을 예측하고, 수문운영이 하류부에 미칠 수 있는 영향을 가시적으로 확인할 수 있었다. 향후 상류의 유량조건 및 상하류 수위차에 따른 가동보의 운영조건이 보 하류의 안정성 지표산정에 활용될 수 있기 위해 보다 심도있는 연구 수행이 필요하다.

• Journal of Advanced Navigation Technology
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• v.23 no.5
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• pp.452-459
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• 2019

In this paper, we describe a PCM encoder structure that can update the telemetry system parameters in real time. In the PCM encoder, an analog signal control unit for FPGA, flash memory, and sensor data acquisition was constructed. UART communication, analog signal control, flash memory control, and frame generation are possible through logic inside FPGA of PCM encoder. UART communication allows the PC to transmit parameter data to the PCM encoder, and flash memory is controlled to update the parameter of the telemetry system in real time and finally the frame is formed. Simulation and verification were performed to confirm whether the parameter data is updated in real time, and the proposed structure was used to construct a telemetry system with enhanced flexibility and convenience.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.5
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• pp.597-608
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• 2021

The control head components used in small military vessels are designed to be domestically produced, prototypes, structural analysis, and casting methods are designed and cast. The control head assembly consists of a lever, an aluminum outside cover, Middle, front gear cover, back gear cover, and a zinc worm gear. In order to reverse the design of each component, 3D scanning device was used, 3D modeling was performed by CATIA, and prototype productions were carried out by 3D printer. In order to reduce the cost of components, gating system is used by gravity casting method. The SRG ratio of 1:0.9:0.6 was set by applying non-pressurized gating system to aluminum parts, 1:2.2:2.0 and pressurized gating system to zinc parts, and the shapes of sprue, runner and gate were designed. The results of porosity were also confirmed by casting analysis in order to determine whether the appropriate gating system can be designed. The results showed that all parts started solidification after filling completely. ANSYS was used for structural analysis, and the results confirmed that all five components had a safety factor of 15 more. All castings are free of defects in appearance, and CT results show only very small porosity. ZnDC1 zinc alloy worm gear has a tensile strength of 285 MPa and an elongation of 8%. The tensile strength of the four components of A356 aluminum alloy is about 137-162 MPa and the elongation is 4.8-6.5%.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.5
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• pp.325-333
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• 2021

A 3 kW grid-tied PV inverter with Gallium nitride high-electron mobility transistor (GaN HEMT) for domestic commercialization was developed using boost converter and full-bridge inverter with LCL filter topology. Recently, many GaN HEMTs are manufactured as surface mount packages because of their lower parasitic inductance characteristic than standard TO (transistor outline) packages. A surface mount packaged GaN HEMT releases heat through either top or bottom cooling method. IGOT60R070D1 is selected as a key power semiconductor because it has a top cooling method and fairly low thermal resistances from junction to ambient. Its characteristics allow the design of a 3 kW inverter without forced convection, thereby providing great advantages in terms of easy maintenance and high reliability. 1EDF5673K is selected as a gate driver because its driving current and negative voltage output characteristics are highly optimized for IGOT60R070D1. An LCL filter with passive damping resistor is applied to attenuate the switching frequency harmonics to the grid-tied operation. The designed LCL filter parameters are validated with PSIM simulation. A prototype of 3 kW PV inverter with GaN HEMT is constructed to verify the performance of the power conversion system. It achieved high power density of 614 W/L and peak power efficiency of 99% for the boost converter and inverter.