• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.39-42
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• 2018

In this paper, a low-power MPPT interface circuit for vibration energy harvesting sources is presented. The designed circuit rectifies the harvested ac type energy to the dc type energy required to drive the system, and periodically samples and holds the open circuit voltage (Voc) through the MPPT controller, and transfers the harvested power to the load while maintaining the input voltage at 1/2 of the maximum available power point. All circuits have been designed using a 0.35-um CMOS technology, and the operation has been verified through simulation. Simulation results show that the designed circuit consumes 98nA of current at 3V input voltage and the maximum power efficiency is 99.21%. The designed chip occupies $1.281mm{\times}1.236mm$.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.235-244
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• 2000

This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.58-70
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• 1990

This paper describes a VLSI implementation of real-time two dimensional DCT processor for the subprimary rate video codec system. The proposed architecture exploits the parallelism and concurrency of the distributes architecture for vector inner product operation of DCT and meets the CCITT performance requirements of video codec for full CSIF 30 frames/sec. It is also shown that this architecture satisfies all the CCITT IDCT accuracy specification by simulating the suggested architecture in bit level. The efficient VLSI disign methodology to design suggested architecture is considered and the module generator oriented design environments are constructed based on SUN 3/150C workstation. Using the constructed design environments. the suggensted architecture have been designed by double metal 2micron CMOS technology. The chip area fo designed 8x8 2-D DA-DCT (Distributed Arithmetic DCT) processor is about 3.9mmx4.8mm.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.6
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• pp.17-25
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• 2004

In this paper, we propose a new small swing domino logic for low-power consumption. To reduce the power consumption, both the precharge node and the output node swing the range from 0 to $V_{REF}$- $V_{THN}$, where $V_{REF}$=VDD-n $V_{THN}$ (n=1, 2, and 3). This can be done by adding the inverter structure on domino logic that allows a full swing or a small swing on its input terminal without leakage current. Compared to previous works, the proposed structure can save the power consumption of more than 30% for n=0, 1, 2, and 3 in the equation of $V_{REF}$=VDD-n $V_{THN}$. A multiplier applying the proposed domino logic has been designed and fabricated using a 0.35-${\mu}{\textrm}{m}$ n-well CMOS process under 3.3-V supply voltage. Compared with other previous works, it shows a 30% power reduction and a better feature in power-delay product.lay product.

• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.531-538
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• 2005

In the high performance Analog Information Processing Systems(AIPS), gain boosting or additional gain stage is required when the gain is not sufficient with one stage amplification. This work shows that high gain is neatly obtained by enhancing the gain using the negative resistance element. Compared to the conventional techniques, the proposed scheme enjoys full output swing, small circuit area and power consumption, and the applications to various configurations of amplifiers. The negative resistance element is placed between the differential output nodes when used in the Op-Amp. The HSPICE simulation indicates that enhancement of more than 40 dB is readily obtained in this simple configuration when the negative resistance element is implemented in the form of cross-coupled CMOS inverters.

• The Transactions of the Korea Information Processing Society
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• v.6 no.7
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• pp.1929-1940
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• 1999

In this paper a VLSI design for the automatic magnetizing and inspection system has been presented. This is a design of a peripheral controller, which magnetizes CRTs and computer monitors and controls the automatic inspection system. We implemented a programmable peripheral interface(PPI) circuit of the control and protocol module for the magnetizer controller by using a 0.8um CMOS SOG technology of ETRI. Most of the PPI functions have been confirmed. In the conventional method, the propagation/ramp delay model was used to predict the delay of cells, but used to model on only a single cell. Later, a modified "linear delay predict model" was suggested in the LODECAP(LOgic DEsign CAPture) by adding some factors to the prior model. But this has not a full model on the delay chain. In this paper a new " delay predict equation" for the design of the timing control block in PPI system has been suggested. We have described the detail method on a design of delay chain block according to the extracted equation and applied this method to the timing control block design. And we had descriptions on the other blocks of this system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.3
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• pp.311-317
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• 2019

We first numerically analyzed the characteristics of a silicon-based grating structure for beam steering. The analysis includes the basic principle of the grating structure according to the wavelength, peak radiation angle, radiation efficiency, and full-width at the half maximum(FWHM) of the radiation angle. Based on the analysis, we propose a silicon-based grating structure integrated with distributed Bragg reflector(DBR) to obtain a high radiation efficiency and narrow beam width simultaneously. We performed the numerical optimization of the radiation efficiency and FWHM of the radiation angle according to the DBR position. By the design optimization using the proposed grating structure compatible with the complementary metal-oxide semiconductor(CMOS) process, we achieved a maximum radiation efficiency of 87.1% and minimum FWHM of radiation angle of $4.68^{\circ}$.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.4
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• pp.671-678
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• 2022

Approximate computing is an computational technique that is acceptable degree of inaccurate results of accurate results. Approximate multiplication is one of the approximate computing methods for high-performance and low-power computing. In this paper, we propose a high-density, low-power, and high-speed approximate multiplier using approximate 4-2 compressor and improved full adder. The approximate multiplier with approximate 4-2 compressor consists of three regions of the exact, approximate and constant correction regions, and we compared them by adjusting the size of region by applying an efficient partial product reduction. The proposed approximate multiplier was designed with Verilog HDL and was analyzed for area, power and delay time using Synopsys Design Compiler (DC) on a 25nm CMOS process. As a result of the experiment, the proposed multiplier reduced area by 10.47%, power by 26.11%, and delay time by 13% compared to the conventional approximate multiplier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.54-60
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• 2007

This paper proposes a built-in-self-repair (BISR) structure using 2-dimensional spare memory to effectively self-repair faults of an embedded memory. In case of multiple faults in the same row (column) of an embedded memory, the previous method using 1-D spare column (row) memory needs the same number of spare memory columns (rows) as the number of faults to self-repair them. while the new method using 2-D spare memory needs only one spare row (column) to self-repair them. Also, the virtual divided memory is adopted to be able to self-repair using not a full spare column memory but the only partial spare column memory corresponding to the faults. A self-repair circuit with $64\times1-bit$ core memory and $2\times8$ 2-D spare memory is designed. And the circuit includes a built-in-self-test block using the 13N March algorithm. The circuit has been implemented using the $0.25{\mu}m$ MagnaChip CMOS process and has $1.1\times0.7mm^2$ chip area with 10,658 transistors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.