• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.11
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• pp.1-10
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• 1993

This paper proposes a High Performance Full-Swing BiCMOS (HiF-BiCMOS) circuit which improves on the conventional BiCMOS circuit. The HiF-BiCMOS circuit has all the merits of the conventional BiCMOS circuit and can realize full-swing logic operation. Especially, the speed of full-swing logic operation is much faster than that of conventional full-swing BiCMOS circuit. And the number of transistors added in the HiF-BiCMOS for full-swing logic operation is constant regardless of the number of logic gate inputs. The HiF-BiCMOS circui has high stability to variation of environment factors such as temperature. Also, it has a preamorphized Si layer was changed into the perfect crystal Si after the RTA. Remarkable scalability for power supply voltage according to the development of VLSI technology. The power dissipation of HiF-BiCMOS is very small and hardly increases about a large fanout. Though the Spice simulation, the validity of the proposed circuit design is proved.

• Journal of the Korean Society of Industry Convergence
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• v.4 no.2
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• pp.199-205
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• 2001

With the growth of BiCMOS technology in ASIC design, the issue of analyzing fault characteristics and testing techniques for BiCMOS circuits become more important In this paper, we analyze the fault models and characteristics of high speed full-swing BiCMOS circuits and the DFT technique to enhance the testability of full-swing high speed BiCMOS circuits is discussed. The SPICE simulation is used to analyze faults characteristics and to confirm the validity of DFT technique.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.1
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• pp.76-82
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• 2002

This paper presents a quaternary-binary decoder, a quaternary logic current buffer, and a quaternary logic full-adder using current-mode multiple-valued logic CMOS circuits. Proposed full-adder requires only 15 MOSFET, 60.5% and 48.3% decrease of devices are achieved compared with conventional binary CMOS full-adder and Current's full-adder. Therefore, decrease of area and internal nods are achieved. Designed circuits are simulated and verified by HSPICE. Proposed full-adder has 1.5 ns of propagation delay and 0.42㎽ of power consumption. Also, proposed full-adder can easily adapted to binary system by use of encoder, designed decoder and designed current buffer.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.467-468
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• 2008

In this paper, a logic family, the transmission gate CMOS(TG CMOS) is proposed, which combines the transmission gate and pass transistor resulting in a different configuration from traditional full CMOS. In the simulation, basic cells comprising this logic are designed and their dynamic responses are analyzed. The simulation shows their performance is exceeding that of conventional full CMOS.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.180-188
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• 2015

As a potential alternative to the complementary metal-oxide semiconductor (CMOS) technology, many researchers are focusing on carbon-nanotube field-effect transistors (CNFETs) for future electronics. However, existing studies report the advantages of CNFETs over CMOS at the device level by using small-scale circuits, or over outdated CMOS technology. In this paper, we propose a methodology of analyzing CNFET-based circuits and study its impact at the full-chip scale. First, we design CNFET standard cells and use them to construct large-scale designs. Second, we perform parasitic extraction of CNFET devices and characterize their timing and power behaviors. Then, we perform a full-chip analysis and show the benefits of CNFET over CMOS in 45-nm and 20-nm designs. Our full-chip study shows that in the 45-nm design, CNFET circuits achieve a 5.91×/3.87× (delay/power) benefit over CMOS circuits at a density of 200 CNTs/µm. In the 20-nm design, CNFET achieves a 6.44×/3.01× (delay/power) benefit over CMOS at a density of 200 CNTs/µm.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.65-72
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• 2013

This paper presents design methodology for Memristor-CMOS circuits and its application to primitive IPs design. We proposed a Memristor model and designed basic elements, Memristor AND/OR gates. The primitive IPs based on a Memristor-CMOS technology is proposed for a Memristive system design. The netlists of IPs are extracted from the layouts of Memristor-CMOS and is verified with SPICE-like Memristor model under $0.18{\mu}m$ CMOS technology. As a result, an example design Memristor-CMOS full adder has only 47.6 % of silicon area compare to the CMOS full-adder.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.275-278
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• 2003

This paper presents a full-adder using current-mode multiple valued logic CMOS circuits. This paper compares propagation delay, power consumption, and PDP(Power Delay Product) compared with conventional circuit. This circuit is designed with a samsung 0.35um n-well 2-poly 3-metal CMOS technology. Designed circuits are simulated and verified by HSPICE. Proposed full-adder has 2.25 ns of propagation delay and 0.21 mW of power consumption.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.126-134
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• 1990

In order to implement high-speed data acquistion system in CMOS VLSI technology, means must be found to overcome the relatively low transconductance and large device mismatch characteristic of MOS device. Because of these device limitations, circuit design approaches tradition-ally used in high-speed bipolar analog-to-digital converter(ADC) are suited to CMOS implementation. Also the design of VLSI CMOS comparator wherein voltage comparision is accomplished by means of a pipelined cascade RSA (Regenerative Sense Amplifier). So, in this paper we designed the A/D converter incorporates the pipelined CMOS comparator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.1-9
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• 2009

A full adders is an important component in applications of digital signal processors and microprocessors. Thus it is imperative to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional static CMOS and pass transistor logic. The carry-out generation circuit of the proposed full adder is different from the conventional XOR-XNOR structure. The output Cout of module III is generated from input A, B and Cin directly without passing through module I as in conventional structure. Thus output Cout is faster by reducing operation step. The proposed module III uses the static CMOS logic style, which results full-swing operation and good driving capability. The proposed 1bit full adder has the advantages over the conventional static CMOS, CPL, TGA, TFA, HPSC, 14T, and TSAC logic. The delay time is improved by 4.3% comparing to the best value known. PDP(power delay product) is improved by 9.8% comparing to the best value. Simulation has been carried out using a $0.18{\mu}m$ CMOS design rule for simulation purposes. The physical design has been verified using HSPICE.

• Journal of IKEEE
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• v.12 no.1
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• pp.1-7
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• 2008

With the recent development of portable system such as mobile communication and multimedia. Full adders are important components in applications such as digital signal processors and microprocessors. Thus It is important to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional Ratioed logic and Pass Transistor logic. The proposed adder has the advantages over the conventional CMOS, TGA, 14T logic. The delay time is improved by 13% comparing to the average value and PDP(Power Delay Product) is improved by 9% comparing to the average value. Layouts have been carried out using a 0.18um CMOS design rule for evaluation purposes. The physical design has been evaluated using HSPICE.