• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.26 no.12
• /
• pp.1108-1111
• /
• 2015

In this paper, a ${\times}49$ frequency multiplier based on a ring oscillator and a multi-push multiplier is presented. The proposed ${\times}49$ frequency multiplier consists of two ${\times}7$ frequency multipliers and these multiplier is connected by injection-locking technique. Each ${\times}7$ frequency multiplier consists of a ring oscillator with 14-phase output signal and 7-push frequency multiplier requiring 14-phase input. The proposed ${\times}49$ frequency multiplier provides 2.78~2.83 GHz output signal with 56.7~57.7 MHz input signal. This operation frequency is defined that the output power difference between the carrier and the spur is above 10 dB. The proposed chip consumes 13.93 mW.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.6
• /
• pp.793-801
• /
• 1993

We show theoretically that the performance characteristics of an external cavity semiconductor laser, such as frequency locking and frequency noise reduction, can be greatly improved by just inserting a high finesse Fabry-Perrot(F-P) etalon inside the external reflector. For example, when the F-P etalon of finesse 30 and optical thickness 1.5cm is inserted inside the external cavity of length 3.0cm, the frequency locking accuracy and the linewidth reduction ration are increased up to 7.6 times and 86 times respectively compared with the conventional external-cavity laser under the same operation condition.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.5
• /
• pp.65-70
• /
• 2008

A novel fast locking dual-loop integer-N phase locked loop(PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a $0.35{\mu}m$ CMOS process with a 3.3V supply voltage. Simulation results show the fast look time of $50{\mu}s$ for an 80MHz frequency jump in a 200KHz channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.8
• /
• pp.717-724
• /
• 2016

This paper presents design of a 40 GHz CMOS PLL frequency synthesizer for a 60 GHz sliding-IF RF transceiver. For stable locking over a wide bandwith for a injection-locked frequency divider, an inductive-peaking technique is employed so that it ensures the PLL can safely lock across the very wide tuning range of the VCO. Also, Injection-locked type LC-buffer with low-phase noise and low-power consumption is added in between the VCO and ILFD so that it can block any undesirable interaction and performance degradation between VCO and ILFD. The PLL is designed in 65 nm CMOS precess. It covers from 37.9 to 45.3 GHz of the output frequency. and its power consumption is 74 mA from 1.2 V power supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.5
• /
• pp.522-527
• /
• 2011

In this work, a 54 GHz divide-by-3 injection-locked frequency divider(ILFD) based on ring oscillator has been developed in a 0.13-${\mu}M$ Si RFCMOS technology for phase-locked loop(PLL) application. The free-running frequency is 18.92~19.31 GHz with tuning range of 0~1.8 V, consuming 70 mW with a 1.8 V supply voltage. At 0 dBm input power, the locking range is 1.02 GHz(54.82~55.84 GHz) and, with varactor tuning of 0~1.8 V, the total operating range is 2.4 GHz(54.82~57.17 GHz). The fabricated circuit size is 0.42 mm${\times}$0.6 mm including probing pads and 0.099 mm${\times}$0.056 mm for core area.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.16 no.10
• /
• pp.914-924
• /
• 1991

It has been generally used for PLL(Phase Locked Loop) to be synthesized randomly chosen frequency state, but the PLL locking time was inevitable element. A direct digital synthesizer. Which makes output frequency directly in sine wave by a phase accumulating method, could be leiminate the defect, although a phase distortion in frequency spectrum. In order to improve this disadvantage, the phase accumulating method is reconsidered in the side of he output wave formula expression. A new mechanism is proposed, and it is constructed by a most suitable logic elements. The spectrum of synthesized sine waveform is simulated and compared with a measured value, and it’s the coherence frequency hoppong state with the PN(Pseudo Noise) code sequence is confirmed. In this results, the power levels of phase distortion harmonics are decreased to 10~25dB and bandwidths are increased to 420kHz.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.1
• /
• pp.9-14
• /
• 2016

This study evaluated a digital locking device design using detection distance of 13.4mm of a human body sensing type magnetic field coil. In contrast to digital locking devices that are used nowadays, the existing serial number entering buttons, lighting, number cover, corresponding pcb, exterior case, and data delivery cables have been deleted and are only composed of control ON/OFF power switches and emergency terminals. When the magnetic field coil substrates installed inside the inner case detects the electric resistance delivered from the opposite side of the 12mm interval exterior contacting the glass body part, the corresponding induced current flows. At this time, the magnetic field coil takes the role as a sensor when coil frequency of the circular coil is transformed. The magnetic coil as a sensor detects a change in the oscillation frequency output before and after the body is detected. This is then amplified to larger than 2,000%, transformed into digital signals, and delivered to exclusive software to compare and search for embedded data. The detection time followed by the touch area of the body standard to a $12.8{\emptyset}$ magnetic field coil was 30% contrast at 0.08sec and 80% contrast at 0.03sec, in which the detection distance was 13.4mm, showing the best level.

• Proceedings of the Korean Magnestics Society Conference
• /
• 2011.06a
• /
• pp.73-74
• /
• 2011

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.1B
• /
• pp.183-192
• /
• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• Korean Journal of Optics and Photonics
• /
• v.5 no.2
• /
• pp.278-285
• /
• 1994

We investigated the spectral characteristics for temperature and driving current change in visible laser diode. As a result of spectrum analysis, the ratio of frequency change for temperature and driving current change were about $33 GHz/^{\circ}C$, 6.6 GHz/mA in the region which was not mode hopping range. Compared to the sharp mode hopping in the near IR single mode AlGaAs lasers, the visible laser diode showed relatively broad multimode operation in the mode hopping region. We performed the experiment of injection-locking characteristics analysis for visible laser diode. Locking half bandwidth(LHBW) was measured 0~5.0 GHz for $0~25\muW$ input power and it was dependent on the input power. Also, LHBW for polarization angle was dependent on the difference of polarization angle between master laser and slave laser. The phase change of injection-locked output beam of the slave laser diode as a function of the drive current was measured in the interferometer which was composed of master laser and slave laser. The ratio of phase change with the slope of 5.0~1.3 rad/mA was obtained within injection-locking range for the change of $2~25\muW$ input power. power.