The Journal of Korean Institute of Electromagnetic Engineering and Science (한국전자파학회논문지)

The Korean Institute of Electromagnetic Engineering and Science (한국전자파학회)
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Design of a 40 GHz CMOS Phase-Locked Loop Frequency Synthesizer Using Wide-Band Injection-Locked Frequency Divider

광대역 주입동기식 주파수 분주기 기반 40 GHz CMOS PLL 주파수 합성기 설계

  • Nam, Woongtae (Department of Wireless Communications Engineering, Kwangwoon University) ;
  • Sohn, Jihoon (Department of Wireless Communications Engineering, Kwangwoon University) ;
  • Shin, Hyunchol (Department of Wireless Communications Engineering, Kwangwoon University)
  • Received : 2016.05.09
  • Accepted : 2016.08.03
  • Published : 2016.09.07
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Abstract

This paper presents design of a 40 GHz CMOS PLL frequency synthesizer for a 60 GHz sliding-IF RF transceiver. For stable locking over a wide bandwith for a injection-locked frequency divider, an inductive-peaking technique is employed so that it ensures the PLL can safely lock across the very wide tuning range of the VCO. Also, Injection-locked type LC-buffer with low-phase noise and low-power consumption is added in between the VCO and ILFD so that it can block any undesirable interaction and performance degradation between VCO and ILFD. The PLL is designed in 65 nm CMOS precess. It covers from 37.9 to 45.3 GHz of the output frequency. and its power consumption is 74 mA from 1.2 V power supply.

본 논문은 60 GHz 슬라이딩-IF 구조 RF 송수신기를 위한 40 GHz CMOS PLL 주파수 합성기 설계를 다룬다. 광대역에서 안정적인 주입동기식 주파수 합성기 동작을 위하여 인덕티브 피킹 기법을 이용한 주파수 분주기가 설계되었다. 광대역 주파수 분주기는 PLL이 전압 제어 발진기의 전체 주파수 범위에서 안정적으로 동기되는 것을 보장한다. 또한, 전압 제어 발진기와 주입동기식 주파수 분주기 사이의 원치 않는 간섭을 없애기 위하여 주입동기식 버퍼를 설계하여 적용하였다. 설계된 PLL 주파수 합성기는 65 nm CMOS 공정을 이용하여 설계되었으며, 37.9~45.3 GHz 출력 주파수 범위를 갖는다. 1.2 V 전원 전압에서 버퍼 포함 74 mA의 전류를 소모한다.

Keywords

References

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