• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.246-248
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• 2007

This paper presents fast locking PLL(Phase Locked Loop) that can improve a jitter noise characteristics and acquisition process by designing a PFD(Phase Frequency Detector) circuit. The conventional PFD has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. The advanced PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, and it has excellent performances such as 1.75us of locking time and independent duty cycle characteristic. It is fabricated in a 0.018-${\mu}m$ CMOS process, and 1.8v supply voltage, and 25MHz of input oscillator frequency, and 800MHz of output frequency and is simulated by using ADE of Cadence.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.4
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• pp.1899-1911
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• 2018

In this work, we propose a concurrency control scheme in object-oriented database (OODB). Since an OODB provides complex modeling power than the conventional relational databases, a concurrency control technique in OODB is also rather complicated and has influence on the overall performance. Thus, it is very important to develop a concurrency control technique with less overhead. The proposed scheme deals with class hierarchy that is a key concept in OODBs. The proposed scheme is developed on implicit locking scheme. Also, the proposed scheme is designed using data access frequency in order to reduce locking overhead than implicit locking. It means that, if access frequency information is not available, the proposed scheme works just like the existing implicit locking, In our work, the correctness of the proposed scheme is proved. The performance is analyzed depending on access types. Also, it is proved that our scheme performs works much better than the implicit locking does.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.95-99
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• 2000

New locking algorithm of DLL is proposed to improve the locking speed and low power dissipation in this paper, In spite of using the architecture of delay controller, low power consumption is acquired by operating only one controller at once and fast locking speed is accomplished by initial setting from the coarse controller. The proposed DLL circuit is operated from 50MHz to 200MHz and locked within 6 cycle at all of operating frequency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.534-542
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• 2017

This paper presents a fast locking technique for a fractional-N PLL frequency synthesizer. The technique directly measures $K_{VCO}$ on a chip, computes the VCO's target tuning voltage for a given target frequency, and directly sets the loop filter voltage to the target voltage before the PLL begins the normal closed-loop locking process. The closed-loop lock time is significantly minimized because the initial frequency of the VCO are put very close to the desired final target value. The proposed technique is realized and designed for a 4.3-5.3 GHz fractional-N synthesizer in 65 nm CMOS and successfully verified through extensive simulations. The lock time is less than $12.8{\mu}s$ over the entire tuning range. Simulation verifications demonstrate that the proposed method is very effective in reducing the synthesizer lock time.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.269-272
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• 2003

A low phase noise frequency synthesizer at X-Band which employs the subharmonic injection locking was designed and tested. The frequency synthesizer consists of two oscillators - master and slave : A 1.75GHz master oscillator made of PLL synthesizer produces 6th harmonic at 10.5GHz, which excites the following 10.5GHz slave oscillator. The realized frequency synthesizer has a 4.5dBm of output power, and a phase noise of -108dBc/Hz at the 100kHz offset frequency.

• Current Optics and Photonics
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• v.2 no.5
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• pp.443-447
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• 2018

We propose a diode-pumped cesium laser using frequency locking of a pump laser that can effectively increase the maximum output power of the cesium laser. We simultaneously monitored the absorption spectrum of cesium and the laser output power, and the frequency of pump laser was locked at the center of the $D_2$ absorption line of the cesium atom to obtain an effective gain enhancement. Using this scheme, we have achieved output power increase of ~0.1 W compared to when frequency locking was not applied. Furthermore, by optimizing the temperature of the cesium cell and the reflectivity of the output coupler, we successfully achieved an output power of 1.4 W using the pump power of 2.9 W, providing a slope efficiency of 61.5% and optical-to-optical efficiency of 49%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.152-158
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• 2004

A low phase noise frequency synthesizer at X-Band which employs the subharmonic injection locking was designed and tested. The designed frequency synthesizer consists of a 1.75 GHz master oscillator - which also operates as a harmonic generator - and a 10.5 GHz slave oscillator. A 1.75 GHz master oscillator based on PLL technique used two transistors - one constitutes the active part of VCO and the other operates as a buffer amplifier as well as harmonic generator. The first stage operates a fixed locked oscillator and using the BJT transistor whose cutoff frequency is 45 GHz, the second stage is designed, operating as a harmonic generator. The 6th harmonic which is produced from the harmonic generator is injected into the following slave oscillator which also behaves as an amplifier having about 45 dB gain. The realized frequency synthesizer has a 7.4 V/49 mA, -0.5 V/4 mA of the low DC power consumption, 4.53 dBm of output power, and a phase noise of -95.09 dBc/Hz and -108.90 dBc/Hz at the 10 kHz and 100 kHz offset frequency, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2378-2384
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• 2009

A novel phase-locked loop(PLL) architecture of sub-micron locking time has been proposed. Input frequency is multiplied by using a delay-locked loop(DLL). The input frequency of a PLL is multiplied while the PLL is out of lock. The multiplied input frequency makes the PLL having a wider loop bandwidth. It has been simulated with a $0.18{\mu}m$ 1.8V CMOS process. The simulated locking time is $0.9{\mu}s$ at 162.5MHz and 2.6GHz, input and output frequency, respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.133-139
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• 1995

In this paper, the frequency separation locking and interval stabilization of 4-channel DFB-LDs have been demonstrated using a fiber Fabry-Perot filter with an free spectral range of 100GHz. Frequency fluctuation and locking range of each channel were appeared to be within 15MHz and over 12GHz, respectively. Back-reflection curve from the fiber Fabry-Perot filter was used for the extraction of an error signal in order to increase the number of accomodable channels and extinction ratio.

• Current Optics and Photonics
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• v.7 no.4
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• pp.443-448
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• 2023

The ±1-order Kelly sidebands with dispersion-dependent spacing of mode-locking fiber lasers are investigated for frequency-tunable terahertz signal generation. The principle of dispersion dependence of Kelly sidebands is analyzed. A new method, which is a dispersion-management mechanism introduced into the fiber-laser cavity, is proposed to generate Kelly sidebands with widely tunable wavelength spacing. A spacing tuning range of up to 28.46 nm of the ±1-order Kelly sidebands is obtained in simulation. Using the data of the optical spectrum with dispersion-dependent Kelly sidebands, the frequency spectrum of generated terahertz signals is calculated. Consequently, the signal frequency can be changed from 0.09 to 2.27 THz.