• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.33-40
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• 1992

The design method of signal delay line system using indirect frequency synthesizer is presented. The variable signal delay line system with 2[nsec] step of delay time at center frequency 60[MHz], bandwidth 500[KHz] and range 5.24-5.81[x10S0-6Tsec] is designed and fabricated. The results were met with good characteristics to be variable delay time of average 2.01[nsec] per step.

• Journal of electromagnetic engineering and science
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• v.12 no.2
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• pp.166-170
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• 2012

This paper presents a tunable composite right/left-handed (CRLH) delay line for a delay line discriminator that linearizes modulated frequency sweep in a frequency modulated continuous wave (FMCW) radar transmitter. The tunable delay line consists of 8 cascaded unit cells with series varactor diodes and shunt inductors. The reverse bias voltage of the varactor diode controlled the group delay through its junction capacitance. The measured results demonstrate a group delay of 8.12 ns and an insertion loss of 4.5 dB at 250 MHz, while a control voltage can be used to adjust the group delay by approximately 15 ns. A group delay per unit cell of approximately 1 ns was obtained, which is very large when compared with previously published results. This group delay can be used effectively in FMCW radar transmitters.

• Journal of Sensor Science and Technology
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• v.3 no.1
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• pp.40-45
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• 1994

$112^{\circ}$ rot. x-cut $LiTaO_{3}$ wafer was used as the substrate of SAW gas sensor. Dual delay line SAW device with IDTs which consist of the reference delay line and the sensing delay line was fabricated using photolithigraphy. Each IDTs had 10 finger pairs and finger spacing is 10 microns. One delay line channel is the reference, while the second is the sensing channel with Pb-phthalocyanine film in the propagation path. Pb-phthalocyanine film which is p-type organic semiconductor was evaporated in $10^{-5}$ torr vacuum using shadow mask selectively. Dual delay line oscillator was constructed by using the rf amplifier and AGC. Frequency of the IDTs had the range of $87{\sim}$89 MHz oscillation frequency. Oscillation frequency shifts were investigated as a function of the temperature and the concentration of $NO_{2}$ gas.

• Current Optics and Photonics
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• v.2 no.1
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• pp.34-38
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• 2018

An X-band microwave photonic (MWP) filter using switch-based fiber-optic delay lines has been proposed and experimentally demonstrated. It is composed of two electro-optic modulators (EOMs) and $2{\times}2$ optical MEMS-switch-based fiber-optic delay lines. By changing time-delay difference and coefficients of each wavelength signal by using fiber-optic delay lines and an electro-optic modulator, respectively, a bandpass filter or a notch filter can be implemented. For an X-band MWP filter with four channel elements, fiber-optic delay lines with the unit time-delay of 50 ps have been experimentally realized and the frequency responses corresponding to the time-delays has been measured. The measured frequency response error at center frequency and the time-delay difference error were 180 MHz at 10 GHz and 3.2 ps, respectively, when the fiber-optic delay line has the time-delay difference of 50 ps.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.259-262
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• 2012

This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.87-90
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• 2000

This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.

• Journal of the Optical Society of Korea
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• v.20 no.2
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• pp.300-304
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• 2016

A dual loop optoelectronic oscillator (OEO) based on an acousto-optic modulator (AOM) for single mode operation with an acousto-optic delay line is demonstrated in this paper. When the OEO operates, the free spectral range is a function of the total loop length of the OEO, which is mainly dependent on the propagation time of the acoustic wave in the AOM. Due to the huge difference in the magnitude between the speed of light and the acoustic velocity in the AOM, the effective loop length converted to light-propagation length of the OEO increases to 3.8 km. With 150 MHz oscillation frequency, phase noise of -118 dBc/Hz at 10 kHz frequency offset, and -140 dBc/Hz at 200 kHz frequency offset, is achieved.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.1
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• pp.42-49
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• 2016

In this paper, we design and fabricate an instantaneous frequency measurement receiver with a frequency resolution of 125 MHz which detects and measures continuous signals in 4~6 GHz using path difference of delay lines. The receiver has a 4-bit configuration and consists of power dividers, delay lines, power combiners, power detectors, voltage comparator circuits and so on. The accuracy of the instantaneous frequency measurement is improved by applying offset voltage compensation to the comparator circuits to compensate the frequency-dependent path loss of the delay line and the frequency dependence of power detection.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.394-397
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• 2003

Since the speed of operation in the system has been increasing rapidly, chips should have been synchronized. Then, synchronized circuits such as PLL (Phase Locked Loop), DLL (Delay Locked Loop) are used. VCO (Voltage Controled Oscillator) generated a frequency in the PLL has disadvantage such as jitter accumulation. On the other hands, VCDL (Voltage Controled Delay Line) used at DLL has an advantage which has no jitter accumulation. In this paper, a new and improved VCDL structure is suggested.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.137-144
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• 2013

A delay-locked loop (DLL) that generates a 32-phase clock with the operating frequency of 125 MHz is introduced. The proposed DLL uses a delay line of $4{\times}8$ matrix architecture to improve a differential non-linearity (DNL) of the delay line. Furthermore, a integral non-linearity (INL) of the proposed DLL is improved by calibrating phases of clocks that is supplied to four points of an input stage of the $4{\times}8$ matrix delay line. The proposed DLL is fabricated by using $0.11-{\mu}m$ CMOS process with a 1.2 V supply. The measured operating frequency range of the implemented DLL is 40 MHz to 280 MHz. At the operating frequency of 125MHz, the measurement results shows that the DNL and INL are +0.14/-0.496 LSB and +0.46/-0.404 LSB, respectively. The measured peak-to-peak jitter of the output clock is 30 ps when the peak-to-peak jitter of the input clock is 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW, respectively.