• Journal of IKEEE
• /
• v.13 no.4
• /
• pp.63-68
• /
• 2009

The power management integrated circuit(PMIC) for CCD image sensor is presented in this study. A CCD image sensor is very sensitive against temperature. The temperature, that is heat, is generally generated by the PMIC with low efficiency. Since the generated heat influences performance of CCD image sensor, it should be minimized by using a PMIC which has a high efficiency. In order to develop the PMIC with high efficiency, the input stage is designed with synchronous type step down DC-DC converter. The operating range of the converter is from 5V to 15V and the converter is controlled using PWM method. The PWM control circuit consists of a saw-tooth generator, a band-gap reference circuit, an error amplifier and a comparator circuit. The saw-tooth generator is designed with 1.2MHz oscillation frequency. The comparator is designed with the two stages OP Amp. And the error amplifier has 40dB DC gain and $77^{\circ}$ phase margin. The output of the step down converter is connected to input stage of the charge pump. The output of the charge pump is connected to input of the LDO which is the output stage of the PMIC. Finally, the PMIC, based on the PWM control circuit and the charge pump and the LDO, has output voltage of 15V, -7.5V, 3.3V and 5V. The PMIC is designed with a 0.35um process.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.19 no.1
• /
• pp.680-687
• /
• 2018

Borehole radar is a radar used for underground resources and geological exploration purposes. It needs a high-speed sampler to transmit electromagnetic waves with a pulse width of several ns and to receive reflected waves of several tens to several hundreds of MHz reflected from the object to be surveyed. ETS (Equivalent-Time Sampling), which can achieve sampling performance of several GHz with a sampling frequency of several tens of MHz, is suitable for use as a sampler of a borehole radar receiver. In this paper, we propose a method to control the sampling clock delay, which is the most important factor in ETS sampler design, using four clocks with phase difference of $90^{\circ}$ for one clock source. The proposed method can reduce the time required to acquire the data within the set interval by 1/25 than the conventional method using the delay generator. When the implemented sampler is applied to the receiver of existing borehole radar, it is possible to accumulate 58 additional times due to the shortened sampling time. In addition, by using one delay control logic compared with the conventional method using several sampling clock delay control logic in order to satisfy the target sampling range, it is possible to omit the correction process which was necessary in the past. As a result, the structure of the system can be simplified and a uniform sampler can be realized.

• Journal of the Korean Society for Nondestructive Testing
• /
• v.21 no.5
• /
• pp.510-517
• /
• 2001

This paper describes an initial study for the application of eddy current pattern recognition approaches to more realistic flaw characterization in steam generator tubes. For this purpose, finite-element model-based theoretical eddy current testing (ECT) signals are simulated from 5 types of OD flaws with the variation in flaw size parameters and testing frequency. In addition, three kinds of software are developed for the convenience in the application of steps in pattern recognition approaches such as feature extraction feature selection and classification by probabilistic neural networks (PNNs). The cross point of the ECT signals simulated from flaws with non-symmetric cross-sections shows the deviation from the origin of the impedance plane. New features taking advantages of this phenomenon are added to complete the feature set with a total of 18 features. Then, classification with PNNs are performed based on this feature set. The PNN classifiers show high performance for the identification of symmetry in the cross-section of a flaw. However, they show very limited success in the interrogation of the sharpness of flaw tips.

• Journal of the Institute of Convergence Signal Processing
• /
• v.9 no.1
• /
• pp.62-74
• /
• 2008

In this paper, we would like to propose the design of symmetric digital filter core in order to use in the radio astronomy. The function of FIR filter core would be designed by VHDL code required at the Data Acquisition System (DAS) of Korean VLBI Network (KVN) based on the FPGA chip of Vertex-4 SX55 model of Xilinx company. The designed digital filter has the symmetric structure to increase the effectiveness of system by sharing the digital filter coefficient. The SFFU(Symmetric FIR Filter Unit) use the parallel processing method to perform the data processing efficiently by using the constrained system clock. In this paper, therefore, for the effective design of SFFU, the Unified Synthesis software ISE Foundation and Core Generator which has excellent GUI environment were used to overall IP core synthesis and experiments. Through the synthesis results of digital filter core, we verified the resource usage is less than 40% such as Slice LUT and achieved the maximum operation frequency is more than 260MHz. We also confirmed the SFFU would be well operated without error according to the SFFU simulation result using the Modelsim 6.1a of Mentor Graphics Company. To verify the function of SFFU, we carried out the additional simulation experiments using the pseudo signal to the Matlab software. From the comparison experimental results of simulation and the designed digital FIR filter, we confirmed the FIR filter was well performed with filter's basic function. So we verified the effectiveness of the designed FIR digital filter with symmetric structure using FPGA and VHDL.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.6
• /
• pp.670-680
• /
• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.

• Korean Chemical Engineering Research
• /
• v.60 no.2
• /
• pp.249-254
• /
• 2022

With the rapid advance of the semiconductor and Information and communication technologies, remote environment monitoring technology, which can detect and analyze surrounding environmental conditions with various types of sensors and wireless communication technologies, is also drawing attention. However, since the conventional remote environmental monitoring systems require external power supplies, it causes time and space limitations on comfortable usage. In this study, we proposed the concept of the self-powered remote environmental monitoring system by supplying the power with the levitation-electromagnetic generator (L-EMG), which is rationally designed to effectively harvest biomechanical energy in consideration of the mechanical characteristics of biomechanical energy. In this regard, the proposed L-EMG is designed to effectively respond to the external vibration with the movable center magnet considering the mechanical characteristics of the biomechanical energy, such as relatively low-frequency and high amplitude of vibration. Hence the L-EMG based on the fragile force equilibrium can generate high-quality electrical energy to supply power. Additionally, the environmental detective sensor and wireless transmission module are composed of the micro control unit (MCU) to minimize the required power for electronic device operation by applying the sleep mode, resulting in the extension of operation time. Finally, in order to maximize user convenience, a mobile phone application was built to enable easy monitoring of the surrounding environment. Thus, the proposed concept not only verifies the possibility of establishing the self-powered remote environmental monitoring system using biomechanical energy but further suggests a design guideline.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.8A
• /
• pp.950-961
• /
• 2004

In this paper, we measured and analyzed propagation characteristics in a subway tunnel that is recently increasingly becoming one of the radio communication environments. The measurements are carried out in a subway tunnel with frequency bands of 2.45㎓ and 5.8㎓. The length of tunnel we used for this study is 175m of LOS (Line-of-sight) and 270m of NLOS (Non Line-of-Sight). The subway tunnel is curved and its cross section is horseshoe type. The measurement systems we employ in this study are a narrow-band system and a wide-band system. The narrow-band system is used to get path loss measurement and the wide-band system is used to figure out delay profile measurement. In particular, the wide-band system consists of 1023 length PN sequence generator using a chip rate of 80MHz based on a sliding correlation technique. The omni-directional antennas and directional antennas are used to analyze propagation characteristics for beam type of antenna. The path loss displays only pure path loss of a tunnel environment. The delay profile indicates the mean excess delay and RMS (root mean square) delay spread.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.7 no.2
• /
• pp.205-213
• /
• 2002

This paper deals with the implementation of three-phase VSI systems which can control the power regenerated from DC bus line to AC supply. The overall system consists of the line-to-line voltage and line current sensors, an actual power calculator using d-q transformation method, a complex power controller with PI control scheme, a gating signal generator for modified ｑ-conduction mode, a DPLL for frequency followup, and Power circuits. Control board is constructed by using a 32-bit DSP TMS32C32, two EFLDs , six ADCs, and a DAC. To verify the performance of the proposed system, we designed and constructed the propotype with the power rating of 5kVA at AC 220V. Experimental results show that the regenerated active power is well controlled to its command vague and the regenerated reactive power still remained at nearly zero through all operating modes.

• Journal of the Korean Society for Precision Engineering
• /
• v.31 no.7
• /
• pp.635-642
• /
• 2014

The large volume multi-tasking vertical lathe was developed for machining the bearing parts for a wind power generator. Although the machined part is large in size high precision tolerances are required recently. One of the most important components to achieve this mission is the rotating table which holds and supports the part to be machined. The oil hydrostatic bearing is adopted for the thrust bearing and the rolling bearing for the radial bearing. In this article experimental performance evaluation and its analysis results are presented. The rotational accuracy of the table is assessed and the frequency domain analysis for the structural loop is performed. And in order to evaluate the structural characteristic of table the moment load experiment is performed. The rotational error motion is measured as below 10 ${\mu}m$ for the radial and axial direction and 22,800 Nm/arcsec of moment stiffness is achieved for the rotary table.

• Journal of the Microelectronics and Packaging Society
• /
• v.17 no.4
• /
• pp.73-76
• /
• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.