• Journal of electromagnetic engineering and science
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• v.4 no.1
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• pp.23-29
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• 2004

In this paper we analyze convergence constraints and time constant of IT-LMS algorithm and derive a method of making it's time constant independent of signal power by using input variance estimation. The method for estimating the input variance is to use a single-pole low-pass filter(LPF) with common smoothing parameter value, θ. The estimator is with narrow bandwidth for large θ but with wide bandwidth for small θ. This small θ gives long term average estimation(low frequency) of the fluctuating input variance well as short term variations (high frequency) of the input power. In our simulations of multipath communication channel equalization environments, the method with large θ has shown not as much improved convergence speed as the speed of the original IT-LMS algorithm. The proposed method with small θ=0.01 reach its minimum MSE in 100 samples whereas the IT-LMS converges in 200 samples. This shows the proposed, tap-power normalized IT-LMS algorithm can be applied more effectively to digital wireless communication systems.

• Journal of the Korea Society of Computer and Information
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• v.14 no.7
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• pp.57-64
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• 2009

Based on this article, I have analyzed the OFDM system which applies three types of equalizer forms in the two-path channel of the microwave baseband. The Two-path channel of microwave baseband had been simulated through the Rummler channel. In the Two-path channel, the OFDM system which has three forms of equalizer has been analyzed and the result is, equalizer 1-tab has great improvement in efficiency compared with Pre-FFT 11-tab which has noise power ratio less than 18dB. On the contrary, if the symbol energy to the noise ratio is more than 18dB, the equalizer which applies Pre-FFT 11-tab has greater efficiency compared to the equalizer which applies 1-tab frequency. Last but not least, the OFDM system which applies Dual equalizer has better efficiency compared to the system which has 1-tab frequency and equalizer which applies Pre-FFT 11-tab.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.465-469
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1471-1479
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• 1999

This paper presents an adaptive beamforming algorithm for an MC-CDMA system with an adaptive array antenna. By employing an antenna array at the receiver of an MC-CDMA system, the performance of an MC-CDMA system, which is known to be effective for high data rate transmission due to its robustness to multipath fading and its simplicity for using a simple one-tap equalizer, is shown to be significantly improved. The proposed algorithm for adaptive beanforming in an MC-CDMA system is derived by (1) calculating the error signals between the pilot symbols of desired user and the received pilot signals in frequency domain, (2) transforming the frequency-domain error signals into time-domain error signals, (3) updating the filter coefficients of the adaptive beamformer in the direction of minimizing the MSE. Convergence behavior and performance improvement of the proposed approach are demonstrated through computer simulation by applying it to the conventional MC-CDMA system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• Journal of Advanced Navigation Technology
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• v.10 no.4
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• pp.394-399
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• 2006

In this paper, we investigated performance for 5.8GHz dedicated short range communication system using OFDM which will be applied to Intelligent transportation system services. The maximum speed of a vehicle in DSRC channel is very fast as 180km/h, so a service time is very short to serve a various traffic information if hand-off is not occurred. Therefore higher bit rate is required to proved advanced and intelligent service to the drivers of various vehicle and the data transmission rate of the next generation DSRC system if being promoted over 10Mbps. The signals received in Clarke & Gans channel have been simulated using the computer simulator.