• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1406_1407
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• 2009

Fowler-Nordheim의 전자 방출과 열전자 방출 메카니즘을 이용하여 절연유체 내 전계에 의한 도체의 음극에서 전자 방출현상과 열에 의한 열전자 방출현상을 고려하고 유한요소법(Finite Element Method)을 이용하여 해석하였다. 절연유체 내 공간전하에 대한 해석기법으로 푸아송 방정식, 양이온, 음이온, 전자에 대한 전하연속 방정식, 온도에 대한 열 확산 방정식으로 이루어진 5개의 지배방정식에 Fowler-Nordheim의 전계 방출과 Richardson-Dushman의 열전자 방출을 경계조건으로 부여하였다. 단자 전류는 유한요소법과 잘 부합하는 에너지법으로 계산되었다. 쌍 곡선형 PDE의 공간전하 전파에 대한 지배 방정식은 일반적으로 수치적인 불안정성을 가지므로 인공 확산 항을 고려하여 이를 해결하였다. 제안된 해석법은 세 개의 캐리어를 가진 x-y 좌표축의 2차원 평판 모델에 적용하여 그 유효성을 확인하였다.

• 한국정보통신학회논문지
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• 제11권12호
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• pp.2361-2365
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• 2007

OLED 소자의 전기적 특성을 온도 변화에 따라 측정을 하였다. OLED 소자는 N,N'-diphenyl-N,N'-bis(3-methylphenyl)-1,1'-diphenyl-4,4'-diamine (TPD)를 정공 수송층으로, tris(8-hydroxyquinoline) aluminum(Alq3)를 전자송층 및 발광층으로 사용하였다. 전압-전류 특성은 온도 범위 $10K{\sim}300K$에서 측정하였다. OLED 소자에서의 전도 메커니즘의 해석은 Fowler-Nordheim tunneling 법을 이용하여 해석하였다.

• 전기학회논문지
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• 제58권10호
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• pp.2011-2015
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• 2009

In an insulating dielectric liquid such as transformer oil, space charge injection and propagation were analyzed under the Fowler-Nordheim and Richardson-Dushman's thermal emission charge injection conditions for blade-plane electrodes stressed by a step voltage. The governing equations were composed of all five equations such as the Poisson's equation for electric fields, three continuity equations for electrons, negative, and positive ions, and energy balanced equation for temperature distributions. The governing equations for each carrier, the continuity equations, belong to the hyperbolic-type PDE of which the solution has a step change at the space charge front resulting in numerical instabilities. To decrease these instabilities, the governing equations were solved simultaneously by the Finite Element Method (FEM) employing the artificial diffusion scheme as a stabilization technique. Additionally, the terminal current was calculated by using the generalized energy method which is based on the Poynting's theorem, and represents more reliable and stable approach for evaluating discharge current. To verify the proposed method, the discharge phenomena were successfully applied to the blade~plane electrodes, where the radius of blade cap was $50{\mu}m$.

• 대한전자공학회논문지
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• 제27권4호
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• pp.541-546
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• 1990

The current conduction and dielectric breakdown properties of oxide grown on phosphorous-doped polysilicon have been investigated by means of the ramped I-V measurements. The effective barrier heights of polyoxide grown by different silicon deposition and oxidation conditions were calculated from the Fowler-Nordheim tunneling characteristic. The average critical fields were also obtained for each film. From the results, the high temperature oxided polyoxide grown on amorphous silicon film shows superior electrical characteristics comparing to the other films.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권1호
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• pp.1-7
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• 2000

The SNOSFET memory devices with ultrathin ONO(tunnel oxide-nitride-blocking oxide) gate dielectric were fabricated using n-well CMOS process and investigated its characteristics. The thicknesses of tunnel oxide, nitride and blocking oxide were $23{\AA},\; 53{\AA}\; and\; 33{\AA}$, respectively. Auger analysis shows that the ONO layer is made up of $SiO_2(upper layer of blocking oxide)/O-rich\; SiO_x\N\_y$. It clearly shows that the converting layer with $SiO_x\N\_y(lower layer of blocking oxide)/N-rich SiO_x\N\_y(nitride)/O-rich SiO_x\N\_y(tunnel oxide)$. It clearly shows that the converting layer with $SiO_x\N\_y$ phase exists near the interface between the blocking oxide and nitride. The programming condition of +8 V, 20 ms, -8 V, 50 ms is determined and data retention over 10 years is obtained. Under the condition of 8 V programming, it was confirmed that the modified Fowler-Nordheim tunneling id dominant charge transport mechanism. The programmed threshold voltage is distributed less than 0.1 V so that the reading error of memory stated can be minimized. An $8\times8$ NAND type flash EEPROM with SONOSFET memory cell was designed and simulated with the extracted SPICE parameters. The sufficient read cell current was obtained and the upper limit of $V_{TH}$ for write state was over 2V.

• KEPCO Journal on Electric Power and Energy
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• 제2권2호
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• pp.223-225
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• 2016

The newly proposed analysis method using a direct-current current-voltage (DCIV) simulation is introduced for investigating leakage current composing MOS transistor. From comparing the density and location of traps using DCIV method and investigating the leakage current of gate channel transistor, we proposed the graphical analysis method to correlate the DCIV current and leakage mechanism by the traps. And, our graphical method intuitively explains that leakage current in MOS transistor is well correlated with the DCIV current of the MOS transistor arrays due to two kinds of traps created by Fowler-Nordheim (F-N) stress and Hot carrier stress, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.691-692
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• 2009

Screen printable CNT pastes were formulated including conductive nano particles (CNPs) and their properties were investigated with an expectation of stable cold cathodes for advanced lamp application. CNT cathodes showed a turn-on field of 1~1.5V/um, a life time of ~100 hours at an emission current density of 10uA/$cm^2$ for DC-bias. Detailed analysis of measured I-V was carried out by applying Fowler-Nordheim model to trace down the origin of emission property degradation.

• 한국전기전자재료학회논문지
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• 제22권11호
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• pp.980-986
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• 2009

In a triple-layered structure of ITO/N,N'-diph enyl-N,N'bis(3-methylphenyl)-1,1' - biphenyl-4,4'-diamine(TPD)/tris(8-hydroxyquinoline)aluminum($Alq_3$)/(2,9-Dimethyl-4,7-diphenyl-1,10-phenanthroline(BCP)/Al device, we have studied the electrical and optical characteristics of organic light-emitting diodes(OLEDs) depending on the deposition condition of BCP layer. Several different sizes of holes on boat and several different deposition rates were employed in evaporating the organic materials. And then, electrical properties of the organic light-emitting diodes were measured and the performance of the devices was analyzed. It was found that the hole-size of crucible boat and the evaporation rate affect on the surface roughness of BCP layer as well as the performance of the device. When the hole-size of crucible boat and the deposition rate of BCP are 1.2 mm and $1.0\;{\AA}/s$, respectively, average surface roughness of BCP layer is lower and the efficiency of the device is higher than the ones made with other conditions. From the analysis of current density-luminance-voltage characteristics of a triple layered device, we divided the conductive mechanism by four region according to applied voltage. So we have obtained a coefficient of ${\beta}_{ST}$ in schottky region is $3.85{\times}10^{-24}$, a coefficient of ${\beta}_{PF}$ in Poole-Frenkel region is $7.35{\times}10^{-24}$, and a potential barrier of ${\phi}_{FN}$ in Fower-Nordheim region is 0.39 eV.

• 한국재료학회지
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• 제4권1호
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• pp.63-74
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• 1994

$SiO_{2}$초박막(ultrathin film)의 두께 조절 용이성, 두께 균일성, 공정 재현성 및 전기적 특성을 향상시키기 위해 실리콘을 $N_{2}O$분위기에서 열산화시켰다. $N_2O$분위기에서 박막 성장시 산화와 동시에 질화가 이루어지기 때문에 전기적 특성의 향상을 가져올 수 있었다. 질화 현상에 의해 형성된 Si-N결합 형성은 습식 식각율과 ESCA분석으로 확인할 수 있었다. $N_2O$분위기에서 성장된 $SiO_{2}$박막은 Fowler-Nordheim(FN)전도 기구를 보여주었으며, 절열파괴 특성과 누설 전류특성 및 산화막의 신뢰성은 건식 산화막에 비해서 우수하였다. 또한 계면 포획밀도는 건식 산화막에 비해 감소하였고, 전하를 주입했을 때 생성되는 계면 준위의 양 또는 크게 감소하였다. 산화막 내부에서의 전하 포획의 양도 감소하였고, 전하를 주입하였을 때 생성되는 전하 포획의 양도 감소하였다. 이와 같은 전기적인 특성의 향상은 산화막 내부에서 약하게 결합하고 있는 Si-O 결합들이 Si-N결합으로의 치환과 스트레스 이완에 의하여 감소하였기 때문이다.

• 한국전기전자재료학회논문지
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• 제21권4호
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• pp.300-304
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• 2008

A novel characterization method was investigated to estimate the trap generation during the program /erase cycles in nand flash memory cell. Utilizing Fowler-Nordheim tunneling current, floating gate potential and oxide electric field, we established a quantitative model which allows the knowledge of threshold voltage (Vth) as a function of either program or erase operation time. Based on our model, the derived results proved that interface trap density (Nit) term is only included in the program operation equation, while both Nit and oxide trap density (Not) term are included in the erase operation equation. The effectiveness of our model was tested using 50 nm nand flash memory cell with floating gate type. Nit and Not were extracted through the analysis of Program/Erase speed with respect to the endurance cycle. Trap generation and cycle numbers showed the power dependency. Finally, with the measurement of the experiment concerning the variation of cell Vth with respect to program/erase cycles, we obtained the novel quantitative model which shows similar results of relationship between experimental values and extracted ones.