• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.79-83
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• 2005

IT 기술, 반도체 산업 등의 급격한 발전에 힘입어 최근의 첨단 전자, 통신제품은 초경량 초소형화와 동시에 고기능 복합화의 발전 추세를 보이고 있다. 이런 추세에 발맞추어 전자제품, 통신제품의 핵심적인 부품인 IC chip도 소형화되고 있다. IC chip 패키징 기술의 하나인 Filp Chip Package는 Module Substrate 위에 Chip Surface를 Bumping 시킴으로서 최단의 접속길이와 저열저항, 저유전율의 특성도 가지면서 초소형에 높은 수율의 저 원가생산성을 갖는 첨단의 패키징 기술이다. 이런 패키징 기술은 수요증가와 더불어 폭발적으로 늘어나고 있으나 까다로운 공정기술에 의해 아직 여러 회사에서 장비가 출시되고 있지 못한 상태이다. 이에 본 연구에서는 최근 수요가 증가하는 LCD Driver IC용 COF 장비를 위한 Flip chip Bonding 장비 및 시스템을 설계, 제작하였다.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.4
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• pp.380-387
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• 2009

The reliability concerns of solder interconnections in flip chip PBGA packages are produced mainly by the mismatch of coefficient of thermal expansion(CTE) between the module and PCB. Finite element analysis has been employed extensively to simulate thermal loading for solder joint reliability and deformation of packages in electronic packages. The objective of this paper is to study the thermo-mechanical behavior of FC-PBGA package assemblies subjected to temperature change, with an emphasis on the effect of the finite element model, material models and temperature conditions. Numerical results are compared with the experimental results by using $moir{\acute{e}}$ interferometry. Result shows that the bending displacements of the chip calculated by the finite element analysis with viscoplastic material model is in good agreement with those by $moir{\acute{e}}$ inteferometry.

• Journal of Welding and Joining
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• v.20 no.2
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• pp.90-94
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• 2002

FC-BGA has advantages over other interconnection methods including high I/O counts, better electrical performance, high throughput, and low profile. But, FC-BGA has a lot of reliability issues. The 2nd level solder joint reliability of the FC-BGA with large chip on laminate substrate was studied in this paper. The purpose of this study is to discuss solder joint failures of 2nd level thermal cycling test. This work has been done to understand the influence of the structure of package, the properties of underfill, the properties and thickness of bismaleimide tiazine substrate and the temperature range of thermal cycling on 2nd level solder joint reliability. The increase of bismaleimide tiazine substrate thickness applied to low modulus underfill was improve of solder joint reliability. The resistance of solder ball fatigue was increased solder ball size in the solder joints of FC-BGA.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.31-35
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• 2013

TSOP(Thin Small Outline Package) is the IC package using lead frame, which is the type of low cost package for white electronics, auto mobile, desktop PC, and so on. Its performance is not excellent compared to BGA or flip-chip CSP, but it has been used mostly because of low price of TSOP package. However, it has been issued in TSOP package that thermal deflection of lead frame occurs frequently during molding process and Au wire between semiconductor die and pad is debonded. It has been required to solve this problem through substituting materials with low CTE and improving structure of lead frame. We focused on developing the lead frame structure having thermal stability, which was carried out by numerical analysis in this study. Thermal deflection of lead frame in TSOP package was simulated with positions of anti-deflection adhesives, which was ranging 198 um~366 um from semiconductor die. It was definitely understood that thermal deflection of TSOP package with anti-deflection adhesives was improved as 30.738 um in the case of inside(198 um), which was compared to that of the conventional TSOP package. This result is caused by that the anti-deflection adhesives is contributed to restrict thermal expansion of lead frame. Therefore, it is expected that the anti-deflection adhesives can be applied to lead frame packages and enhance their thermal deflection without any change of substitutive materials with low CTE.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.121-145
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• 2001

Chip Size Packages (CSP) are now widely used in high speed DRAM. The major driving farce of CSP development is its superior electrical performance than that of conventional package. However, the power dissipation of high speed DRAM like DDR or RAMBUS DRAM chip reaches up to near 2W. This fact makes the thermal management methods in DRAM package be more carefully considered. In this study, the thermal performances of 3 type CSPs named $\mu-BGA$^{TM}$$ $UltraCSP^{TM}$ and OmegaCSP$^{TM}$ were measured under the JEDEC specifications and their thermal characteristics were of a simulation model utilizing CFD and FEM code. The results show that there is a good agreement between the simulation and measurement within Max. 10% of $\circledM_{ja}$. And they show the wafer level CSPs have a superior thermal performance than that of $\mu-BGA.$ Especially the analysis results show that the thermal performance of wafer level CSPs are excellent fur modulo level in real operational mode without any heat sink.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.111-129
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• 2005

Pop provides OEMs and EMS with a platform to cost effectively expand options for logic + memory 3D integration - Expands device options by simplifying business logistics of stacking - Integration controlled at the system level to best match stacked combinations with system requirements - Eliminates margin stacking and expands technology reuse - Helps manage the huge cost impacts associated with increasing demand for multi media processing and memory. PoP is well timed to enable and leverage: - Mass customization of systems for different use (form, fit and function) requirements o Bband and apps processor + memory stack platforms - Logic transition to flip chip enables PoP size reduction o Area and height reduction. Industry standardization is progressing. Amkor provides full turn-key support for base package, memory package and full system integration.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.889-895
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• 2002

Wafer level packaging is gain mote momentum as a low cost, high performance solution for RF-MEMS devices. In this work, the flip-chip method was used for the wafer level packaging of RF-MEMS devices on the quartz substrate with low losses. For analyzing the EM (electromagnetic) characteristic of proposed packaging structure, we got the 3D structure simulation using FEM (finite element method). The electric field distribution of CPW and hole feed-through at 3 GHz were concentrated on the hole and the CPW. The reflection loss of the package was totally below 23 dB and the insertion loss that presents the signal transmission characteristic is above 0.06 dB. The 4-inch Pyrex glass was used as a package substrate and it was punched with air-blast with 250${\mu}{\textrm}{m}$ diameter holes. We made the vortical feed-throughs to reduce the electric path length and parasitic parameters. The vias were filled with plating gold. The package substrate was bonded with the silicon substrate with the B-stage epoxy. The loss of the overall package structure was tested with a network analyzer and was within 0.05 dB. This structure can be used for wafer level packaging of not only the RF-MEMS devices but also the MEMS devices.

• Proceedings of the KWS Conference
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• 2006.05a
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• pp.218-220
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• 2006

Sn-3.0Ag-0.5Cu solder is widely used as micro-joining materials of flip chip package(FCP) because of the fact that it causes less dissolution and has good thermal fatigue property. However, compared with ternary electroplating in the manufacturing process, binary electroplating is still used in industrial field because of easy to make plating solution and composition control. The objective of this research is to fabricate Sn-3.0Ag-0.5Cu solder bumping having accurate composition. The ternary Sn-3.0Ag-0.5Cu solder bumping could be made on a Cu pad by sequent binary electroplating of Sn-Cu and Sn-Ag. Composition of the solder was estimated by EDS and ICP-OES. The thickness of the bump was measured using SEM and the microstructure of intermetallic-compounds(IMCs) was observed by SEM and EDS. From the results, contents of Ag and CU found to be at $2.7{\pm}0.3wt%\;and\;0.4{\pm}0.1wt%$, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.1-6
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• 2014

Flip chip bonded LED packages possess lower thermal resistance than wire bonded LED packages because of short thermal path. In this study, thermal and bonding properties of flip chip bonded high brightness LED were evaluated for Au-Sn thermo-compression bonded LEDs and Sn-Ag-Cu reflow bonded LEDs. For the Au-Sn thermo-compression bonding, bonding pressure and bonding temperature were 50 N and 300oC, respectively. For the SAC solder reflow bonding, peak temperature was $255^{\circ}C$ for 30 sec. The shear strength of the Au-Sn thermo-compression joint was $3508.5gf/mm^2$ and that of the SAC reflow joint was 5798.5 gf/mm. After the shear test, the fracture occurred at the isolation layer in the LED chip for both Au-Sn and SAC joints. Thermal resistance of Au-Sn sample was lower than that of SAC bonded sample due to the void formation in the SAC solder.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.39-43
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• 2009

In this paper, the flow characteristics of underfill material driven by capillary action between flip-chip and substrate were investigated. Also, the effects of viscosity level and dispensing point of underfill on flow characteristics were investigated. Flip chip package size was $5mm{\times}5mm{\times}0.65^tmm$, the diameter of solder bump was 100 ${\mu}m$, and the pitch was 150 ${\mu}m$. It was full grid area-array type with 1024 I/Os. The glass substrate was used and the gap between the chip and substrate was 50 ${\mu}m$. For the experimental study, three different underfills with different viscous properties($2000{\sim}3700$ cps), and two different types of dispensing methods(center dot and edge dot) were used. The flow characteristics and filling time of underfill were investigated by using CCD camera. The results show that the edge flow was faster than center flow due to the edge effect, which was caused by the resistance of solder bumps. In case of edge dot dispensing type, the filling time was faster due to the large edge effect, compared to center dot dispensing type. Also, it was found that the underfill flow was faster and the filling time decreased as the viscosity level of underfill was decreased.