• Proceedings of the Korea Information Processing Society Conference
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• 2006.11a
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• pp.183-186
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• 2006

NPC(Non playable Character)모델은 온라인 게임뿐만 아니라 가상공간 시스템 구축 시 빠질 수 없는 중요한 요소이다. 현재 가장 널리 사용되는 인공지능 처리방식의 하나인 FSM(Finite State Machine)은 NPC의 행동양식을 표현하기 위해 유한한 개수의 상태를 이용하는 알고리즘이다. 인공지능이 적용된 NPC 모델 설계시 정확한 명세는 구현 단계에서 발생되는 자원의 손실을 막아주고 요구명세에 따른 검증을 가능하게 한다. 본 논문에서는 해저가상공간 구축 시 발생되는 어류 객체의 행동패턴을 분석하여 속성을 정의하였으며, 환경변화에 따른 행동 특성의 상호관계를 설정하여 정형화하였다. 정의된 속성을 가진 NPC 모델을 FSM 알고리즘을 적용해 설계하고 구현한다. 설계된 NPC모델은 CTL기반의 모델체커인 SMV(Symbolic Model Verification)를 통해 검증함으로써 설계에 대한 타상성을 입증하였다.

• The Transactions of the Korea Information Processing Society
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• v.5 no.3
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• pp.741-750
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• 1998

본 논문에서는 형식 기법을 이용하여 차세대 지능망 응용 프로토콜(INAP:Intelligent Network Application Protocool)적합성 시험 스위트를 생성하는 방법 및 IUT(Implenentation Under Test)시뮬레이터를 구축하여 시험을 수행함으로써 시험 스위트를 검증하는 방법에 관해 기술한다. SDL(Specification and Description Language)과 같은 형식 언어를 사용하여 INAP FSM(Finite State Machine)을 모델링하고 MSC(Message Sequence Chart)로 시험 목적을 기술한다. 기술된 FSM모델과 시험 목적을 검증하기 위해 모의 시험을 거치며, 검증이 완료된 후 시험 스위트로 변환이 된다. 형식 기법을 이용하여 INAP규격을 정확하게 기술할 수 있을 뿐 아니라 시험 스위트를 자동으로 생성함으로써 시간과 비용을 절감할 수 있다. 또한 생성된 시험 스위트를 시험기에 탑재하여 IUT시뮬레이터를 대상으로 시험을 수행함으로써 시험 스위트를 검증할 수 있는 방안을 제시하였다.

• Korean Journal of Computational Design and Engineering
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• v.13 no.3
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• pp.209-216
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• 2008

This paper presents a novel approach to design evaluation of portable consumer electronic (PCE) products using augmented reality (AR) based tangible interaction and functional behavior simulation. In the approach, the realistic visualization is acquired by overlaying the rendered image of a PCE product on the real world environment in real-time using computer vision based augmented reality. For tangible user interaction in an AR environment, the user creates input events by touching specified regions of the product-type tangible object with the pointer-type tangible object. For functional behavior simulation, we adopt state transition methodology to capture the functional behavior of the product into a markup language-based information model, and build a finite state machine (FSM) to controls the transition between states of the product based on the information model. The FSM is combined with AR-based tangible objects whose operation in the AR environment facilitates the realistic visualization and functional simulation of the product, and thus realizes faster product design and development. Based on the proposed approach, a product design evaluation system has been developed and applied for the design evaluation of various PCE products with highly encouraging feedbacks from users.

• The KIPS Transactions:PartD
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• v.13D no.1 s.104
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• pp.117-124
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• 2006

Hardware and software codesign framework called PeaCE(Ptolemy extension as a Codesign Environment) was developed. It allows to express both data flow and control flow which is described as fFSM which extends traditional finite state machine. While the fFSM model provides lots of syntactic constructs for describing control flow, it has a lack of their formality and then difficulties in verifying the specification. In order to define the formal semantics of the fFSM, in this paper, firstly the hierarchical structure in the model is flattened and then the step semantics is defined. As a result, some important bugs such as race condition, ambiguous transition, and circulartransition can be formally detected in the model.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.5
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• pp.59-68
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• 2005

A novel immunotronic approach to fault detection in hardware based on symbiotic evolution is proposed in this paper. In the immunotronic system, the generation of tolerance conditions corresponds to the generation of antibodies in the biological immune system. In this paper, the principle of antibody diversity, one of the most important concepts in the biological immune system, is employed and it is realized through symbiotic evolution. Symbiotic evolution imitates the generation of antibodies in the biological immune system morethan the traditional GA does. It is demonstrated that the suggested method outperforms the previous immunotronic methods with less running time. The suggested method is applied to fault detection in a decade counter (typical example of finite state machines) and MCNC finite state machines and its effectiveness is demonstrated by the computer simulation.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.300-310
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• 2007

The Session Initiation Protocol (SIP) is one of the major protocols used in call-setup over IP telephony. The SIP-signaled calls use many-sided states according to a request of user. In this paper, we suggest seven states and some events that help developers to design and implement new applications efficiently. And they enable an object-oriented design of the system. If you design the call-setup procedure only by the processing model suggested in RFC 3261 over commercial network, a fatal error may occur in the system because of heavy data traffic or unpredicted exception cases. However, according to the suggested seven states, if they are predefined events in the current system state, the standardized processing routine is executed. Otherwise, they can be processed by the exception routine in system. All event processing routines are designed and implemented using Finite State Machine (FSM).

• Journal of the Korea Society for Simulation
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• v.16 no.4
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• pp.23-31
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• 2007

Anti-Air Warfare(AAW) functionality of the naval combat system is the key functionality to ensure the ship's survivability. We have applied a novel method using model-based-simulation to analyze and design AAW functionality of the Patrol Killer Experimemnt Combat System. In this approach, an AAW functional model is described with the FSM(Finite State Machine) and directly executed for the AAW simulation. After prototyping using model based simulation, Hardware In Loop Simulation(HILS) is conducted as the AAW functionality is interfaced with the other ones of the combat system for completing the integration of the system components. This incremental and iterative development approach based on the model based simulation can minimize the development risks and costs caused by the system complexity for military system, bringing out the merit of the rapid prototyping.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.87-95
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• 2014

This paper describes a dual channel receiver design for CIS interfaces. Each channel includes CTLE(Continuous Time Linear Equalizer), sampler, deserializer and clocking circuit. The clocking circuit is composed of PLL, PI and CDR. Fast lock acquisition time, short latency and better jitter tolerance are achieved by adding OSPD(Over Sampling Phase Detector) and FSM(Finite State Machine) to PI-based CDR. The CTLE removes ISI caused by channel with -6 dB attenuation and the lock acquisition time of the CDR is below 1 baud period in frequency offset under 8000ppm. The voltage margin is 368 mV and the timing margin is 0.93 UI in eye diagram using 65 nm CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1914-1919
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• 2021

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.2
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• pp.193-199
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• 2014

In this paper, we present an overview of the structure of a lab-built powered knee prosthesis and the control of it. We build a powered prosthesis prototype on the basis of previous researches and aim at obtaining the essential technology related with its control. We adopt the slider-crank mechanism with a DC motor as an actuator to manipulate the knee joint. We also build an embedded control system for the prosthesis with a 32-bit DSP controller as a main computation unit. We divide the gait phase into five stages and use a FSM (Finite State Machine) to generate a torque reference needed for each stage. We also propose to use a position-based impedance controller for driving the powered knee prosthesis stably. We perform some walking experiments at fixed speeds on a tread mill in order to show the feature of the built powered prosthesis. The experimental results show that our prosthesis has the ability to provide a functional gait that is representative of normal gait biomechanics.