• Title/Summary/Keyword: Few atomic layer channel

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Remote O2 plasma functionalization for integration of uniform high-k dielectrics on large area synthesized few-layer MoSe2

  • Jeong, Jaehun;Choi, Yoon Ho;Park, Dambi;Cho, Leo;Lim, Dong-Hyeok;An, Youngseo;Yi, Sum-Gyun;Kim, Hyoungsub;Yoo, Kyung-Hwa;Cho, Mann?Ho
    • Proceedings of the Korean Vacuum Society Conference
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    • 2016.02a
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    • pp.281.1-281.1
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    • 2016
  • Transition metal dichalcogenides (TMDCs) are promising layered structure materials for next-generation nano electronic devices. Many investigation on the FET device using TMDCs channel material have been performed with some integrated approach. To use TMDCs for channel material of top-gate thin film transistor(TFT), the study on high-k dielectrics on TMDCs is necessary. However, uniform growth of atomic-layer-deposited high-k dielectric film on TMDCs is difficult, owing to the lack of dangling bonds and functional groups on TMDC's basal plane. We demonstrate the effect of remote oxygen plasma pretreatment of large area synthesized few-layer MoSe2 on the growth behavior of Al2O3, which were formed by atomic layer deposition (ALD) using tri-methylaluminum (TMA) metal precursors with water oxidant. We investigated uniformity of Al2O3 by Atomic force microscopy (AFM) and Scanning electron microscopy (SEM). Raman features of MoSe2 with remote plasma pretreatment time were obtained to confirm physical plasma damage. In addition, X-ray photoelectron spectroscopy (XPS) was measured to investigate the reaction between MoSe2 and oxygen atom after the remote O2 plasma pretreatment. Finally, we have uniform Al2O3 thin film on the MoSe2 by remote O2 plasma pretreatment before ALD. This study can provide interfacial engineering process to decrease the leakage current and to improve mobility of top-gate TFT much higher.

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The Change of I-V Characteristics by Gate Voltage Stress on Few Atomic Layered MoS2 Field Effect Transistors (수 원자층 두께의 MoS2 채널을 가진 전계효과 트랜지스터의 게이트 전압 스트레스에 의한 I-V 특성 변화)

  • Lee, Hyung Gyoo;Lee, Gisung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.31 no.3
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    • pp.135-140
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    • 2018
  • Atomically thin $MoS_2$ single crystals have a two-dimensional structure and exhibit semiconductor properties, and have therefore recently been utilized in electronic devices and circuits. In this study, we have fabricated a field effect transistor (FET), using a CVD-grown, 3 nm-thin, $MoS_2$ single-crystal as a transistor channel after transfer onto a $SiO_2/Si$ substrate. The $MoS_2$ FETs displayed n-channel characteristics with an electron mobility of $0.05cm^2/V-sec$, and a current on/off ratio of $I_{ON}/I_{OFF}{\simeq}5{\times}10^4$. Application of bottom-gate voltage stresses, however, increased the interface charges on $MoS_2/SiO_2$, incurred the threshold voltage change, and degraded the device performance in further measurements. Exposure of the channel to UV radiation further degraded the device properties.

A Study on the Spatial Resolution of Gas Detectors Based on EGS4 Calculations

  • Moon, B.S.;Han, S.H.;Kim, Y.K.;Chung, C.E.
    • Journal of Radiation Protection and Research
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    • v.29 no.1
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    • pp.25-31
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    • 2004
  • Results of EGS4 based calculations to study the spatial resolution of gas detectors are described. The calculations include radial distribution of electrons generated by photons of various energies penetrating into variable thickness of Ar and Xe gas layers. Given a desired spatial resolution, the maximum allowed thickness of gas layer for each energy level is determined. In order to obtain 0.1mm spatial resolution, the maximum thickness for the Ar gas is found to be 2mm for photon energies below 14keV while the optimum energy of photons for Xe gas with the same thickness is about 45keV. The results of calculations performed to compare the number of electrons generated by CsI coated micro-channel plate and the number of electrons generated by the Ar and Xe gas layers are described. The results show that the number of electrons generated by the gases is about 10 times higher than the one generated by CsI coated micro-channel plate. A few sample gray scale images generated by these calculations are included.

Fabrication of Micron-sized Organic Field Effect Transistors (마이크로미터 크기의 유기 전계 효과 트랜지스터 제작)

  • Park, Sung-Chan;Huh, Jung-Hwan;Kim, Gyu-Tae;Ha, Jeong-Sook
    • Journal of the Korean Vacuum Society
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    • v.20 no.1
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    • pp.63-69
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    • 2011
  • In this study, we report on the novel lithographic patterning method to fabricate organic thin film field effect transistors (OTFTs) based on photo and e-beam lithography with well-known silicon technology. The method is applied to fabricate pentacene-based organic field effect transistors. Owing to their solubility, sub-micron sized patterning of P3HT and PEDOT has been well established via micromolding in capillaries and inkjet printing techniques. Since the thermally deposited pentacene cannot be dissolved in solvents, other approach was done to fabricate pentacene FETs with a very short channel length (~30 nm), or in-plane orientation of pentacene molecules by using nanometer-scale periodic groove patterns as an alignment layer for high-performance pentacene devices. Here, we introduce $Al_2O_3$ film grown via atomic layer deposition method onto pentacene as a passivation layer. $Al_2O_3$ passivation layer on OTFTs has some advantages in preventing the penetration of water and oxygen and obtaining the long-term stability of electrical properties. AZ5214 and ma N-2402 were used as a photo and e-beam resist, respectively. A few micrometer sized lithography patterns were transferred by wet and dry etching processes. Finally, we fabricated micron sized pentacene FETs and measured their electrical characteristics.

Fabrication of sub-micron sized organic field effect transistors

  • Park, Seong-Chan;Heo, Jeong-Hwan;Kim, Gyu-Tae;Ha, Jeong-Suk
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.84-84
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    • 2010
  • In this study, we report on the novel lithographic patterning method to fabricate organic-semiconductor devices based on photo and e-beam lithography with well-known silicon technology. The method is applied to fabricate pentacene-based organic field effect transistors. Owing to their solubility, sub-micron sized patterning of P3HT and PEDOT has been well established via micromolding in capillaries (MIMIC) and inkjet printing techniques. Since the thermally deposited pentacene cannot be dissolved in solvents, other approach was done to fabricate pentacene FETs with a very short channel length (~30nm), or in-plane orientation of pentacene molecules by using nanometer-scale periodic groove patterns as an alignment layer for high-performance pentacene devices. Here, we introduce the atomic layer deposition of $Al_2O_3$ film on pentacene as a passivation layer. $Al_2O_3$ passivation layer on OTFTs has some advantages in preventing the penetration of water and oxygen and obtaining the long-term stability of electrical properties. AZ5214 and ma N-2402 were used as a photo and e-beam resist, respectively. A few micrometer sized lithography patterns were transferred by wet and dry etching processes. Finally, we fabricated sub-micron sized pentacene FETs and measured their electrical characteristics.

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Development of a Photoemission-assisted Plasma-enhanced CVD Process and Its Application to Synthesis of Carbon Thin Films: Diamond, Graphite, Graphene and Diamond-like Carbon

  • Takakuwa, Yuji
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.08a
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    • pp.105-105
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    • 2012
  • We have developed a photoemission-assisted plasma-enhanced chemical vapor deposition (PAPE-CVD) [1,2], in which photoelectrons emitting from the substrate surface irradiated with UV light ($h{\nu}$=7.2 eV) from a Xe excimer lamp are utilized as a trigger for generating DC discharge plasma as depicted in Fig. 1. As a result, photoemission-assisted plasma can appear just above the substrate surface with a limited interval between the substrate and the electrode (~10 mm), enabling us to suppress effectively the unintended deposition of soot on the chamber walls, to increase the deposition rate, and to decrease drastically the electric power consumption. In case of the deposition of DLC gate insulator films for the top-gate graphene channel FET, plasma discharge power is reduced down to as low as 0.01W, giving rise to decrease significantly the plasma-induced damage on the graphene channel [3]. In addition, DLC thickness can be precisely controlled in an atomic scale and dielectric constant is also changed from low ${\kappa}$ for the passivation layer to high ${\kappa}$ for the gate insulator. On the other hand, negative electron affinity (NEA) of a hydrogen-terminated diamond surface is attractive and of practical importance for PAPECVD, because the diamond surface under PAPE-CVD with H2-diluted (about 1%) CH4 gas is exposed to a lot of hydrogen radicals and therefore can perform as a high-efficiency electron emitter due to NEA. In fact, we observed a large change of discharge current between with and without hydrogen termination. It is noted that photoelectrons are emitted from the SiO2 (350 nm)/Si interface with 7.2-eV UV light, making it possible to grow few-layer graphene on the thick SiO2 surface with no transition layer of amorphous carbon by means of PAPE-CVD without any metal catalyst.

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