• Korean Journal of Materials Research
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• v.10 no.3
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• pp.199-203
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• 2000

$Ta_2_O5$ and $Sr_0.8Bi_2.4Ta_2O_9$ films were deposited on p-type Si(100) substrates by a rf-magnetron sputtering and the metal organic decomposition (MOD), respectively.The electrical characteristics of the $Pt/SBT/Ta_2O_5/Si$ structure were obtained as the functions of $O_2$ gas flow ratio during the $Ta_2_O5$ sputtering and $Ta_2_O5$ thickness. And to certify the role of $Ta_2_O5$ as a buffer layer, the electrical characteristics of $Pt/SBT/Ta_2O_5/Si$ were compared. $Pt/SBT/Ta_2O_5/Si$ capacitor with 20% $O_2$ gas flow ratio during the $Ta_2_O5$ sputtering did now show typical C-V curve of metal/ferroelectric/insulator/semiconductor (MFIS) structure. The capacitor with 20% $O_2$ gas flow ratio during the $Ta_2_O5$ sputtering had the largest memory window. And the memory window was decreased as the $Ta_2_O5$ gas flow ratio during the $Ta_2_O5$ sputtering was increased to 40%, 60%. In the C-V characteristics of the $Pt/SBT/Ta_2O_5/Si$ capacitors with the different $Ta_2_O5$ thickness, the capacitor with 26nm thickness of $Ta_2_O5$ had the largest memory window. The C-V and leakage current characteristics of the Pt/SBT/Si structure were worse than those of $Pt/SBT/Ta_2O_5/Si$ structure. These results and Auger electron spectroscopy (AES) measurement showed that $Ta_2_O5$ films as a buffer layer tool a role to prevent from the formation of intermediate phase and interdiffusion between SBT and Si.

• Journal of the Korean Vacuum Society
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• v.9 no.3
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• pp.258-262
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• 2000

$YMnO_3$thin films are deposited on Si(100) and $Y_2O_3/Si(100)$ substrate by radio frequency sputtering. The deposition condition of oxygen partial pressure and annealing temperature have significant influences on the preferred orientation of $YMnO_3$film and the size of memory window. The results of x-ray diffraction show that the film deposited in the oxygen partial pressure of 0% is highly oriented along c-axis after annealing at $870^{\circ}C$ for 1 hr in oxygen ambient. However, the films deposited on Si and $Y_2O_3/Si$ in the oxygen partial pressures of 20% show $Y_2O_3$ peak, the excess $Y_2O_3$ in the $YMnO_3$film suppresses the c-axis oriented crystallization. Especially memory windows of the $Pt/YMnO_3/Y_2O_3/Si$ capacitor are 0.67~3.65 V at applied voltage of 2~12 V, which is 3 times higher than that of the film deposited on $Y_2O_3/Si$ in 20% oxygen (0.19~1.21 V) at the same gate voltage because the film deposited in 0% oxygen is well crystallized along c-axis.

• Korean Journal of Materials Research
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• v.7 no.3
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• pp.175-179
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• 1997

bliniaturization oi microwave circuit components is an important issue with the development in the mobile communication. Capacitors, inductors anti hybrid devices of these are building blocks of electric circuits, and the fabrication of these devices using thin film technology will influence on the miniaturization of electronic devices In this paper, we report the successful fabrication of the inductors, capacitors and LC hybrid devices using a ferroelectric and a ferromagnetic oxide thin iilm. Au, stable at high temperatures in oxidizing ambient, is patterned by lift-off process, and oxide thin films are deposited by ion beam sputtering and chemical vapor deposition. These devices are characterized by a network analyzer in 0.5-15GtIz range We got the inductance of 5nH, capacitance oi 10, 000 pF and resonant frequencies of $10^{6}-10^{9}Hz$.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.8 no.4
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• pp.599-604
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• 1998

We have investigated Pt and $RuO_2$ as a bottom electrode for ferroelectric capacitor applications. The bottom electrodes were prepared by using an RF magnetron sputtering method. Some of the investigated parameters were a substrate temperature, gas flow rate, RF power for the film growth, and post annealing effect. The substrate temperature strongly influenced the surface morphology and resistivity of the bottom electrodes as well as the film crystallographic structure. XRD results on Pt films showed a mixed phase of (111) and (200) peak for the substrate temperature ranged from RT to $200^{\circ}C$, and a preferred (111) orientation for $300^{\circ}C$. From the XRD and AFM results, we recommend the substrate temperature of $300^{\circ}C$ and RF power 80W for the Pt bottom electrode growth. With the variation of an oxygen partial pressure from 0 to 50%, we learned that only Ru metal was grown with 0~5% of $O_2$ gas, mixed phase of Ru and $RuO_2$ for $O_ 2$ partial pressure between 10~40%, and a pure $RuO_2$ phase with $O_2$ partial pressure of 50%. This result indicates that a double layer of $RuO_2/Ru$ can be grown in a process with the modulation of gas flow rate. Double layer structure is expected to reduce the fatigue problem while keeping a low electrical resistivity. As post anneal temperature was increased from RT to $700^{\circ}C$, the resistivity of Pt and $RuO_2$ was decreased linearly. This paper presents the optimized process conditions of the bottom electrodes for memory device applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.6
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• pp.436-441
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• 1998

$Pt/SrTiO_3/Pb_x(Zr_{0.52}, Ti_{0.48})O_3/SrTiO_3/Si$ structure was prepared by rf-magnetron sputtering method for use in nondestructive read out ferroelectric RAM(NDRO-FEAM). PBx(Zr_{0.52}Ti_{0.48})O_3}$(PZT) and $SrTiO_3$(STO) films were deposited respectively at the temperatures of $300^{\circ}C and 500^{\circ}C$on p-Si(100) substrate. The role of the STO film as a buffer layer between the PZT film and the Si substrate was studied using X-ray diffraction (XRD), Auger electron spectroscopy (ASE), and scanning electron microscope(SEM). Structural analysis on the interfaces was carried out using a cross sectional transmission electron microscope(TEM). For PZT/Si structure, mostly Pb deficient pyrochlore phase was formed due to the serious diffusion of Pb into the Si substrate. On the other hand, for STO/PZT/STO/Si structure, the PZT film had perovskite phase and larger grain size with a little Pb interdiffusion. the interfaces of the PZT and the STO film, of the STO film and the interface layer and $SiO_2$, and of the $SiO_2$ and the Si substate had a good flatness. Across sectional TEM image showed the existence of an amorphous layer and $SiO_2$ with 7nm thickness between the STO film and the Si substrate. The electrical properties of MIFIS structure was characterized by C-V and I-V measurements. By 1MHz C-V characteristics Pt/STO(25nm)/PZT(160nm)/STO(25nm)/Si structure, memory window was about 1.2 V for and applied voltage of 5 V. Memory window increased by increasing the applied voltage and maximum voltage of memory window was 2 V for V applied. Memory window decreased by decreasing PZT film thickness to 110nm. Typical leakage current was abour $10{-8}$ A/cm for an applied voltage of 5 V.

• Korean Journal of Materials Research
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• v.11 no.1
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• pp.27-33
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• 2001

The growth characteristics of 4-fold grain which was appeared in KLN deposition on $Pt/Ti/SiO_2/Si(100)$ substrate was studied by varying process variables. Substrate temperature, sputtering pressure, rf power were selected as process variables, and experiment was carried out near optimum fabrication condition. When using K and Li enriched target, the optimum fabrication conditions were substrate temperature of $600^{\circ}C$, sputtering pressure of 150mTorr, rf power of 100 W and its surface morphology is sensitively varied by small deposition condition changes. KLN is composed of elements which have large difference of boiling point. And it is difficult to fabricate thin film at high temperature and high vacuum deposition condition. Furthermore the phenomenon during deposition process can not be explained by using Thorton's model which explains the relation between thin film structure and melting point of thin film materials. These phenomenon can be explained using boiling point of elements which consist of thin film material.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.319-322
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• 2003

To match the charge induced by the insulators $CeO_2$ with the remanent polarization of ferro electric SBT thin films, areas of Pt/SBT/Pt (MFM) and those of $Pt/CeO_2/Si$ (MIS) capacitors were ind ependently designed. The area $S_M$ of MIS capacitors to the area $S_F$ of MFM capacitors were varied from 1 to 10, 15, and 20. Top electrode Pt and SBT layers were etched with for various area ratios of $S_M\;/\;S_F$. Bottom electrode Pt and $CeO_2$ layers were respectively deposited by do and rf sputtering in-situ process. SBT thin film were prepared by the metal orgnic decomposition (MOD) technique. $Pt(100nm)/SBT(350nm)/Pt(300nm)/CeO_2(40nm)/p-Si$ (MFMIS) gate structures have been fabricated with the various $S_M\;/\;S_F$ ratios using inductively coupled plasma reactive ion etching (ICP-RIE). The leakage current density of MFMIS gate structures were improved to $6.32{\times}10^{-7}\;A/cm^2$ at the applied gate voltage of 10 V. It is shown that in the memory window increase with the area ratio $S_M\;/\;S_F$ of the MFMIS structures and a larger memory window of 3 V can be obtained for a voltage sweep of ${\pm}9\;V$ for MFMIS structures with an area ratio $S_M\;/\;S_F\;=\;6$ than that of 0.9 V of MFS at the same applied voltage. The maximum memory windows of MFMIS structures were 2.28 V, 3.35 V, and 3.7 V with the are a ratios 1, 2, and 6 at the applied gate voltage of 11 V, respectively. It is concluded that ferroelectric gate capacitors of MFMIS are good candidates for nondestructive readout-nonvolatile memories.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.4
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• pp.427-432
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• 2024

The polymer crystallization process, promoting the formation of ferroelectric β-phase, is essential for developing polyvinylidene fluoride (PVDF)-based high-performance piezoelectric energy harvesters. However, traditional high-temperature annealing is unsuitable for the manufacture of flexible piezoelectric devices due to the thermal damage to plastic components that occurs during the long processing times. In this study, we investigated the feasibility of introducing a flash lamp annealing that can rapidly induce the β-phase in the PVDF layer while avoiding device damage through selective heating. The flash light-irradiated PVDF films achieved a maximum β-phase content of 76.52% under an applied voltage of 300 V and an on-time of 1.5 ms, a higher fraction than that obtained through thermal annealing. The PVDF-based piezoelectric energy harvester with the optimized irradiation condition generates a stable output voltage of 0.23 V and a current of 102 nA under repeated bendings. These results demonstrate that flash lamp annealing can be an effective process for realizing the mass production of PVDF-based flexible electronics.