• 디지털산업정보학회논문지
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• 제12권2호
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• pp.7-14
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• 2016

In this paper presents a low power algorithm using a feasible cluster generation method considered glitch. The proposed algorithm is a method for reducing power consumption of a given circuit. The algorithm consists of a feasible cluster generation process and glitches removal process. So that glitches are not generated for the node to which the switching operation occurs most frequently in order to reduce the power consumption is a method for generating a feasible cluster. A feasible cluster generation process consisted of a node value set, dividing the node, the node aligned with the feasible cluster generation. A feasible cluster generation procedure is produced from the highest number of nodes in the output. When exceeding the number of OR-terms of the inputs of the selected node CLB prevents the signal path is varied by the evenly divided. If there are nodes with the same number of outputs selected by the first highest number of nodes in the input produces a feasible cluster. Glitch removal process removes glitches through the path balancing in the same manner as [5]. Experimental results were compared with the proposed algorithm [5]. Number of blocks has been increased by 5%, the power consumption was reduced by 3%.

• 디지털콘텐츠학회 논문지
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• 제13권1호
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• pp.37-41
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• 2012

본 논문에서는 소모 전력을 최소화하기 위한 FPGA 알고리즘을 제안하였다. 제안한 알고리즘은 FPGA를 구성하고 있는 CLB에 맞도록 회로 분할을 수행하여 매핑 가능 클러스터를 생성한다. 매핑 가능 클러스터는 글리치 제거 방법을 이용하여 소모전력을 감소시킨다. 글리치 제거는 매핑 가능 클러스터의 내부에 대해 신호의 흐름을 분석하여 글리치가 발생될 수 있는 경로에 지연 버퍼 삽입 방법을 이용하여 제거한다. 매핑 가능 클러스터에 대한 글리치를 제거한 후 전체 매핑 가능 클러스터들에 대한 신호 경로를 분석한다. 분석된 결과에 따라 매핑 가능 클러스터 사이의 글리치도 지연 버퍼 삽입 방법을 이용하여 제거한다. 실험은 [8]와 [9] 알고리즘을 대상으로 소모 전력을 비교하였다. 비교결과 [9]에 비해 전체 소모전력이 7.14% 감소되어 알고리즘의 효율성을 입증하였다.

• 디지털산업정보학회논문지
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• 제5권3호
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• pp.69-75
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• 2009

In this paper, we proposed CPLD low power algorithm using reduce glitch power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within CPLD. Glitch removal process using delay buffer insertion method for feasible cluster. Also, glitch removal process using same method between feasible clusters. The proposed method is examined by using benchmarks in SIS, it compared power consumption to a CLB-based CPLD low power technology mapping algorithm for trade-off and a low power circuit design using selective glitch removal method. The experiments results show reduction in the power consumption by 15% comparing with that of and 6% comparing with that of.

• 한국자동차공학회논문집
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• 제12권6호
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• pp.135-142
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• 2004

The severe frontal crash tests are NCAP with belted occupant at 35mph and FMVSS 208 with unbelted occupant at 25mph, This paper describes the design process of occupant protection systems, airbag and seat belt, under the two tests. In this study, NCAP simulations are performed by Monte Carlo search method and cluster analysis. The Monte Carlo search method is a global optimization technique and requires execution of a series of deterministic analyses, The procedure is as follows. 1) Define the region of interest 2) Perform Monte Carlo simulation with uniform distribution 3) Transform output to obtain points grouped around the local minima 4) Perform cluster analysis to obtain groups that are close to each other 5) Define the several feasible design ranges. The several feasible designs are acquired and checked under FMVSS 208 simulation with unbelted occupant at 25mph.

• Journal of information and communication convergence engineering
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• 제5권2호
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• pp.131-135
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• 2007

In this paper, The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1165-1168
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• 2003

In this paper, a CLB-based CPLD low-power technology mapping algorithm is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. Therefore the proposed algorithm is proved an efficient algorithm for a low power CPLD technology mapping.

• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.59-63
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• 2007

In this paper, a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• 디지털콘텐츠학회 논문지
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• 제14권1호
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• pp.1-5
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• 2013

본 논문은 효율적인 CPLD 저전력 알고리즘을 제안하였다. 제안한 알고리즘은 DAG를 이용한 그래프 분할 방식을 적용하였다. 주어진 회로를 DAG로 표현한 후 각각의 노드의 값을 설정하여 회로를 구현하고자 하는 CPLD의 구성 요소에 맞도록 매핑 가능 클러스터를 생성한다. 생성된 매핑 가능 클러스터의 OR 텀수와 입력 변수의, 출력 변수의 수를 고려하여 매핑 가능 클러스터의 소모 전력 값을 구한다. 생성된 매핑 가능 클러스터와 소모 전력 값을 고려하여 소모전력이 최소가 되는 매핑 가능 클러스터를 선정하여 회로를 구현한다. 실험은 [9]와 비교하였으며, 소모전력이 감소되어 알고리즘의 효율성이 입증되었다. 논문에서는 소모 전력을 위한 FPGA 알고리즘을 제안하였다.

• 한국지능시스템학회논문지
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• 제5권2호
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• pp.58-69
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• 1995

본 논문에서는 자기조정 퍼지제어기의 한 설계기법을 제안하고, 이를 전력계통 안정화에 적용하였다. 제안된 퍼지제어기의 파라미터는 최급강하법에 의하여 멤버쉽 함수의 중심치와 폭이 최적인 값으로 자지고정 되어진다. 이를 전력계통에 적용한 결과 제안된 제어기법이 종래의 제어기법보다 응답특성이 우수함을 보였다.

• Bulletin of the Korean Chemical Society
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• 제13권5호
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• pp.482-486
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• 1992

Ion-molecule reactions of acetylene and mixed acetylene-ammonia cluster ions are studied using an electron impact time-of-flight mass spectrometer. The present results clearly demonstrate that $(C_2H_2)_n^+$ cluster ion distribution represents a distinct magic number of n=3. The mass spectroscopic evidence for the enhanced structural stabilities of $[C_6H_4{\cdot}(NH_3)_m]^+$ (m=0-8) ions is also found along with the detection of mixed cluster $[(C_2H_2)_n{\cdot}(NH_3)_m]^+$ ions, which gives insight into the feasible structure of solvated ions. This is rationalized on the basis of the structural stability for acetylene clusters and the dissociation dynamics of the complex ion under the presence of solvent molecules.