디지털산업정보학회논문지 (Journal of Korea Society of Digital Industry and Information Management)

  • 제12권2호
  • /
  • Pages.7-14
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  • 2016
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  • 1738-6667(pISSN)
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  • 2713-9018(eISSN)
디지털산업정보학회 (Korea Society of Digital Industry and Information Management)
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글리치를 고려한 매핑가능 클러스터 생성 방법을 이용한 저전력 알고리즘

The Low Power Algorithm using a Feasible Clustert Generation Method considered Glitch

  • 김재진 (강동대학교 신재생에너지과)
  • 투고 : 2016.05.16
  • 심사 : 2016.06.07
  • 발행 : 2016.06.30
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초록

In this paper presents a low power algorithm using a feasible cluster generation method considered glitch. The proposed algorithm is a method for reducing power consumption of a given circuit. The algorithm consists of a feasible cluster generation process and glitches removal process. So that glitches are not generated for the node to which the switching operation occurs most frequently in order to reduce the power consumption is a method for generating a feasible cluster. A feasible cluster generation process consisted of a node value set, dividing the node, the node aligned with the feasible cluster generation. A feasible cluster generation procedure is produced from the highest number of nodes in the output. When exceeding the number of OR-terms of the inputs of the selected node CLB prevents the signal path is varied by the evenly divided. If there are nodes with the same number of outputs selected by the first highest number of nodes in the input produces a feasible cluster. Glitch removal process removes glitches through the path balancing in the same manner as [5]. Experimental results were compared with the proposed algorithm [5]. Number of blocks has been increased by 5%, the power consumption was reduced by 3%.

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참고문헌

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