• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.2007-2012
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• 2011

To reduce huge computation in the block matching, this paper proposes a fast block matching algorithm which limits search points in the search area. On the basis of two facts that most motion vectors are located in central part of search area and matching error is monotonic decreasing toward the best similar block, the proposed algorithm moves a matching pattern between steps by the one pixel, predicts the motion direction for the best similar block from similar blocks decided in previous steps, and limits movements of search points to ${\pm}45^{\circ}C$ on it. As a result, it could remove the needless search points and reduce the block matching computation. In comparison with the conventional similar algorithms, the proposed algorithm caused the trivial image degradation in images with fast motion but kept the equivalent image quality in images with normal motion, and it, meanwhile, reduced from about 20% to over 67% of the their block matching computation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.1417-1423
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• 1995

In this paper, we propose a full-search block-matching algorithm with early retirement, which can be applied to a 1-D systolic array of processing elements (PE's) for fast motion estimation. In the proposed algorithm, a PE is retired when its current accumulated sum is equal to or larger than the current minimum MAD. If all PE's are retired, the MAD calculation is stopped for the current array position and is started for the next one in the search window. Simulation results show that the optimum motion vector is always found with less computation, the total computation cycles for motion estimation are decreased to about 60%, and the power dissipation in the PE's is reduced to about 40-60%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.10
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• pp.1845-1852
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• 2008

The key elements of inter prediction are motion estimation(ME) and motion compensation(MC). Motion estimation is to find the optimum motion vectors, not only by using a distance criteria like the SAD, but also by taking into account the resulting number of 비트s in the 비트 stream. Motion compensation is compensate for movement of blocks of current frame. Inter-prediction Encoding is always the main bottleneck in high-quality streaming applications. Therefore, in real-time streaming applications, dedicated hardware for executing Inter-prediction is required. In this paper, we studied a motion estimator(ME) for H.264/AVC. The designed motion estimator is based on 2-D systolic array and it connects processing elements for fast SAD(Sum of Absolute Difference) calculation in parallel. By providing different path for the upper and lower lesion of each reference data and adjusting the input sequence, consecutive calculation for motion estimation is executed without pipeline stall. With data reuse technique, it reduces memory access, and there is no extra delay for finding optimal partitions and motion vectors. The motion estimator supports variable-block size and takes 328 cycles for macro-block calculation. The proposed architecture is local memory-free different from paper [6] using local memory. This motion estimation encoder can be applicable to real-time video processing.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.2 s.314
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• pp.74-81
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• 2007

In this paper, an efficient SAD(Sum of Absolute Differences) processor structure for motion estimation of H.264 is proposed. SAD processors are commonly used both in full search methods for motion estimation and in fast search methods for motion estimation. Proposed structure consists of SAD calculator block, combinator block, and minimum value calculator block. Especially, proposed structure is simplified by using Distributed Arithmetic for addition operation. The Verilog-HDL(Hard Description Language) coding and FPGA(Field Programmable Gate Array) implementation results for the proposed structure show 39% and 32% gate count reduction in comparison with those of the conventional structure, respectively. Due to its efficient processing scheme, the proposed SAD processor structure can be widely used in size dominant H.264 chip.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.1
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• pp.64-70
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• 2011

In an H.264/AVC video encoder, the motion estimation at fractional pixel accuracy improves a coding efficiency and image quality. However, it requires additional computation overheads for fractional search and interpolation, and thus, reducing the computation complexity of fractional search becomes more important. This paper proposes a Pixel Re-composition Fractional Motion Estimation (PRFME) algorithm for an H.264/AVC video encoder. Fractional Motion Estimation performs interpolation for the overlapped pixels which increases the computational complexity. PRFME can reduce the computational complexity by eliminating the overlapped pixel interpolation. Compared with the fast full search, the proposed algorithm can reduce 18.1% of computational complexity, meanwhile, the maximum PSNR degradation is less than 0.067dB. Therefore, the proposed PRFME algorithm is quite suitable for mobile applications requiring low power and complexity.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.49-55
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• 2007

To improved the multi-resolution fast hierarchical motion estimation by using de-interlacing algorithm that is effective in term of both performance and VLSI implementation, is proposed so as to cover large search area field-based as well as frame based image processing in SoC design. In this paper, we have simulated a various picture mode M=2 or M=3. As a results, the proposed algorithm achieved the motion estimation performance PSNR compare with the full search block matching algorithm, the average performance degradation reached to -0.7dB, which did not affect on the subjective quality of reconstructed images at all. And acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.26-28
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• 2007

The motion estimation is the most important technique in the image compression of the video standards. In the case of next generation standards in the video codec as H.264, a high compression-efficiency can be also obtained by using a motion compensation. To obtain the accurate motion search, a motion estimation should be achieved up to 1/2 pixel and 1/4 pixel uiuts. To do this, the computational complexity is increased although the image compression rate is increased. Therefore, in this paper, we propose the advanced sub-pixel block matching algorithm to reduce the computational complexity by using a statistical characteristics of SAD(Sum of Absolute Difference). Generally, the probability of the minimum SAD values is high when searching point is in the distance 1 from the reference point. Thus, we reduced the searching area and then we can overcome the computational complexity problem. The main concept of proposed algorithm, which based on TSS(Three Step Search) method, first we find three minimum SAD points which is in integer distance unit, and then, in second step, the optimal point is in 1/2 pixel unit either between the most minimum SAD value point and the second minimum SAD point or between the most minimum SAD value point and the third minimum SAD point In third step, after finding the smallest SAD value between two SAD values on 1/2 pixel unit, the final optimized point is between the most minimum SAD value and the result value of the third step, in 1/2 pixel unit i.e., 1/4 pixel unit in totally. The conventional TSS method needs an eight.. search points in the sub-pixel steps in 1/2 pixel unit and also an eight search points in 1/4 pixel, to detect the optimal point. However, in proposed algorithm, only total five search points are needed. In the result. 23 % improvement of processing speed is obtained.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.11
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• pp.2191-2203
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• 2011

In this paper, we propose a fast and robust algorithm for fighting behavior detection based on Motion Vectors (MV), in order to solve the problem of low speed and weak robustness in traditional fighting behavior detection. Firstly, we analyze the characteristics of fighting scenes and activities, and then use motion estimation algorithm based on block-matching to calculate MV of motion regions. Secondly, we extract features from magnitudes and directions of MV, and normalize these features by using Joint Gaussian Membership Function, and then fuse these features by using weighted arithmetic average method. Finally, we present the conception of Average Maximum Violence Index (AMVI) to judge the fighting behavior in surveillance scenes. Experiments show that the new algorithm achieves high speed and strong robustness for fighting behavior detection in surveillance scenes.

• Journal of the Korea Computer Industry Society
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• v.4 no.10
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• pp.731-740
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• 2003

Since motion estimation remove the redundant data to employ the temporal correlations between adjacent frames in a video sequence, it plays an important role in digital video coding. And in the block matching algorithm, search patterns of different shapes or sizes and the distribution of motion vectors have a large impact on both the searching speed and the image quality. In this paper, we propose a new fast block matching algorithm using the small-cross search pattern and the block-based gradient descent search pattern. Our algorithm first finds the motion vectors that are close to the center of search window using the small-cross search pattern, and then quickly finds the other motion vectors that are not close to the center of search window using the block-based gradient descent search pattern. Through experiments, compared with the block-based gradient descent search algorithm(BBGDS), the proposed search algorithm improves as high as 26-40% in terms of average number of search point per motion vector estimation.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2006.07a
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• pp.403-403
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• 2006